Hi Mark ------ for git-log ------ 8< ------ 8< ------ 8< ------ Renesas Sound has ADG for clock control. Basically it needs accurately divisible external input clock. But sometimes sometimes it doesn't have to be accurate for some reason. We can use ADG clk_i for such case. It came from CPG as very high rate clock, but is not accurately divisible for 48kHz/44.1kHz rate, but enough for approximate rate. This patch set support such use case. ------ extra info ------ 8< ------ 8< ------ 8< ------ 8< ------ Kuninori Morimoto (5): ASoC: rsnd: enable clk_i approximate rate usage ASoC: rsnd: setup clock-out only when all conditions are right ASoC: rsnd: tidyup brga/brgb default value ASoC: rsnd: remove default division of clock out ASoC: rsnd: setup BRGCKR/BRRA/BRRB on rsnd_adg_clk_control() sound/soc/sh/rcar/adg.c | 68 +++++++++++++++++++++++++++++++++-------- 1 file changed, 55 insertions(+), 13 deletions(-) -- 2.25.1
