On 7/26/23 12:48 AM, John Watts wrote:
Hello there! I have an interesting problem that I'm trying to solve. It will require writing adding driver support but right now I'm struggling to understand how I should go about it all. As a background, this is with the Allwinner D1 or T113. It has a 16 channel I2S controller and each channel can be configured to use a specific pin and TDM time slice. Even channels are low LRCLK, odd are high LRCLK. So for my situation I want to have six channels: - Channel 0: Timeslot 0, Pin 0, LRCLK 0 -> ADC 1 - Channel 1: Timeslot 0, Pin 0, LRCLK 1 -> ADC 1 - Channel 2: Timeslot 0, Pin 1, LRCLK 0 -> ADC 2 - Channel 3: Timeslot 0, Pin 1, LRCLK 1 -> ADC 2 - Channel 4: Timeslot 0, Pin 2, LRCLK 0 -> ADC 3 - Channel 5: Timeslot 0, Pin 2, LRCLK 1 -> ADC 3
It would help if you described what those different 'channels' are supposed to transmit. Usually channels mean a group of data that is rendered at the same time. It looks like you plan on transmitting independent streams that may be enabled/disabled separately.
Also you should describe if there are independent clocks or if all those 6 'channels' are transmitted with a single pair of bit/frame clocks? That completely changes the model, in the former case you could represent independent DAIs/dailinks but in the latter case you really have a single muxed stream.
