topology: nhlt: intel: support m/n divider and xtal/cardinal/pll clock source

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alsa-project/alsa-utils pull request #220 was edited from brentlu:

Current alsatplg supports only cardinal clock source without m/n divider. Code in SOF ssp driver is ported here to implement the divider function.

I tested the code on ADL brya device with following setting:
MCLK: 19.2MHz
BCLK: 3.072Mz (m 24 n 25)

Request URL   : https://github.com/alsa-project/alsa-utils/pull/220
Patch URL     : https://github.com/alsa-project/alsa-utils/pull/220.patch
Repository URL: https://github.com/alsa-project/alsa-utils



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