Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> writes: > On 10/05/2023 13:23, Aidan MacDonald wrote: >> ... >> + ess,max-clock-div: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: >> + Sets the maximum MCLK divider for generating the internal CLK. >> + CLK must be at least 20x the I2C bus speed or I2C transactions >> + will fail. The maximum divider should be chosen to ensure that >> + CLK will not fall below the limit. >> + enum: >> + - 1 >> + - 2 >> + - 4 >> + - 8 >> + default: 1 > > Why do you need to customize it per board? > There's no generic API to read or change the bus speed (SCL frequency) for I2C adapters, so it's impossible to calculate a limit on the MCLK divider automatically. Defaulting to 1 is always safe, but means wasting power at lower sample rates. If you know what the bus speed is you can use a higher divider limit to save power, and it has to be done at the board/firmware level because that's the only place where the bus speed is known. >> + >> + ess,oscillator-pad-bias: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: Sets the oscillator pad drive bias. 0 - full bias, 15 - disabled. >> + minimum: 0 >> + maximum: 15 >> + default: 0 >> + >> +required: >> + - compatible >> + - reg >> + - "#sound-dai-cells" >> + - avdd-supply >> + - vcca-supply >> + - avcc3v3-supply >> + - avcc1v8-supply >> + - clocks >> + - clock-names >> + - reset-gpios >> + >> +additionalProperties: false > > Instead: unevaluatedProperties: false > > >> + >> +examples: > > Best regards, > Krzysztof Everything else agreed, I'll send v2 later today. Regards, Aidan
