On 2/8/23 10:09 AM, Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx> wrote:
On Tue, Feb 07, 2023 at 04:25:24PM +0000, Lucas Tanure wrote:
> Shared boost allows two amplifiers to share a single boost
> circuit by communicating on the MDSYNC bus.
> The passive amplifier does not control the boost and receives
> data from the active amplifier.
>
> Shared Boost is not supported in HDA Systems.
> Based on David Rhodes shared boost patches.
>
> Signed-off-by: Lucas Tanure <lucas.tanure@xxxxxxxxxxxxx>
> ---
> -int cs35l41_global_enable(struct regmap *regmap, enum cs35l41_boost_type b_type, int enable)
> +int cs35l41_global_enable(struct regmap *regmap, enum cs35l41_boost_type b_type, int enable,
> + struct completion *pll_lock)
> {
> int ret;
> + unsigned int gpio1;
>
> switch (b_type) {
> + case CS35L41_SHD_BOOST_ACTV:
> + case CS35L41_SHD_BOOST_PASS:
> + regmap_update_bits(regmap, CS35L41_PWR_CTRL3, CS35L41_SYNC_EN_MASK, 0);
> +
> + gpio1 = enable ? CS35L41_GPIO1_MDSYNC : CS35L41_GPIO1_HIZ;
> + regmap_update_bits(regmap, CS35L41_GPIO_PAD_CONTROL, CS35L41_GPIO1_CTRL_MASK,
> + gpio1 << CS35L41_GPIO1_CTRL_SHIFT);
> +
> + ret = regmap_update_bits(regmap, CS35L41_PWR_CTRL1, CS35L41_GLOBAL_EN_MASK,
> + enable << CS35L41_GLOBAL_EN_SHIFT);
> + usleep_range(3000, 3100);
> + if (!enable)
> + break;
> +
> + if (!pll_lock)
> + return -EINVAL;
> +
> + ret = wait_for_completion_timeout(pll_lock, msecs_to_jiffies(1000));
> + if (ret == 0) {
> + ret = -ETIMEDOUT;
> + } else {
> + regmap_update_bits(regmap, CS35L41_PWR_CTRL3, CS35L41_SYNC_EN_MASK, 0);
Its wrong here. Should be enabling it not disable.
I will send v3.
> + regmap_update_bits(regmap, CS35L41_PWR_CTRL1, CS35L41_GLOBAL_EN_MASK,
> + 0 << CS35L41_GLOBAL_EN_SHIFT);
> + usleep_range(3000, 3100);
> + regmap_update_bits(regmap, CS35L41_PWR_CTRL1, CS35L41_GLOBAL_EN_MASK,
> + 1 << CS35L41_GLOBAL_EN_SHIFT);
> + usleep_range(3000, 3100);
> + }
This approach also makes me nervous, I was somewhat imagining the
usage of regmap_multi_reg_write for this sequence was because it
was very important that no other register writes could interleave
in between these writes. But I don't know, so it could also have
just been a random design choice. So we probably need David to
confirm if that was the reason for the original code here.
Thanks,
Charles
