On Wed, Dec 21, 2022 at 06:38:16PM +0100, Emanuele Ghidoli wrote: > On 21/12/2022 17:56, Charles Keepax wrote: > >On Tue, Dec 20, 2022 at 08:12:23PM +0100, Emanuele Ghidoli wrote: > >>On 20/12/2022 11:00, Charles Keepax wrote: > >>>On Mon, Dec 19, 2022 at 04:20:10PM +0100, Emanuele Ghidoli wrote: > >>>>On 19/12/2022 10:58, Charles Keepax wrote: > >>>>>On Sat, Dec 17, 2022 at 12:47:14AM +0100, Emanuele Ghidoli wrote: > In every case the volume updates, while playing, when you write the relevant register > (raw i2cset or changing volume using amixer). > >Yeah that is not quite what I was getting at. I am wondering if > >volume updates work whilst CP_DYN_PWR==0 and CLK_SYS_ENA==1. > Why are you wondering? It should be a standard working case (obviously > with MCLK running). I know, from datasheet, that: > "CLK_SYS_ENA = 1 and MCLK is not present, then register access will be > unsuccessful". But it is not our case. Apologies yes I was intending for MCLK to be on as well, but I think we have covered this test condition with your "In every case the volume updates, while playing" comment above. > Watching another codec driver (wm8964: see out_pga_event comment) and > the Startup-sequence (of WM8904) in datasheet we figure out that volume > update must be done after PGA enable. > I tested another patch, I'm pretty convinced that it is the right way to > do it. Now it is working in all conditions (even Class G with disabled bypass). > Maybe some hw guy in Cirrus Logic can dig around? > Anyway, this is the tested patch, that, to me, sound good: > Yeah this patch looks better, as you say tracks with the datasheet and other CODECs of the same era have a similar requirement. I think if send this one as a separate patch we can go with that and feel free to add my ack: Acked-by: Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx> Thanks, Charles
