On Thu, Dec 15, 2022 at 10:36:14AM +0100, Lukasz Majewski wrote:
> This patch enables support for internal wm8940's PLL and proper
> divider to set proper value for 256x fs clock.
>
> This approach is more flexible and replaces hardcoded clock
> values and makes the codec work with the simple-card driver.
> Card drivers calling set_pll() and set_clkdiv() directly are
> unaffected.
>
> For the reference - code in this commit is based on:
> "ASoC: wm8974: configure pll and mclk divider automatically"
> (SHA1: 51b2bb3f2568e6d9d81a001d38b8d70c2ba4af99).
Minor nit this doesn't quite match the commit <12-chars of SHA>
("<description>") format in Submitting-patches.rst.
>
> Signed-off-by: Lukasz Majewski <lukma@xxxxxxx>
> ---
But the patch looks good to me:
Acked-by: Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx>
Thanks,
Charles
