On 12/12/2022 03:43, Trevor Wu (吳文良) wrote: >>> >>>>> + uniqueItems: true >>>>> + items: >>>>> + minimum: 0 >>>>> + maximum: 15 >>>>> + >>>>> + "^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$": >>>>> + description: Specify etdm in mclk output rate for always >>>>> on >>>>> case. >>>> >>>> How is it different than assigned-clock-rates? >>>> >>> >>> This includes clock enabling at init stage. >> >> assigned-clock-rates are also at init stage. I asked what is >> different. >> > > If the property is used, there are three parts included in dai driver > probe function. > > 1. set clock parent (which APLL) > 2. set clock rate (MCLK rate) > 3. enable clock (MCLK On) > > The first two parts can be done by existing dts clock properties, but > the last one can't. > When MCLK should be enabled at boot time and kept on, this property is used. That's why I say the property is designed for always-on case. Heh, so the "always on case" means this property enables clock? How is this even DT property? That's not how clocks should be kept enabled. You need proper clock provider and consumer. Best regards, Krzysztof
