From: Luca Ceresoli <luca.ceresoli@xxxxxxxxxxx> Add device tree bindings document for the internal audio codec of the Rockchip RK3308 SoC. Signed-off-by: Luca Ceresoli <luca.ceresoli@xxxxxxxxxxx> --- .../bindings/sound/rockchip,rk3308-codec.yaml | 102 ++++++++++++++++++ MAINTAINERS | 6 ++ .../dt-bindings/sound/rockchip,rk3308-codec.h | 15 +++ 3 files changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/rockchip,rk3308-codec.yaml create mode 100644 include/dt-bindings/sound/rockchip,rk3308-codec.h diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3308-codec.yaml b/Documentation/devicetree/bindings/sound/rockchip,rk3308-codec.yaml new file mode 100644 index 000000000000..f3458f86ef06 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rockchip,rk3308-codec.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/rockchip,rk3308-codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3308 Internal Codec + +description: | + This is the audio codec embedded in the Rockchip RK3308 + SoC. It has 8 24-bit ADCs and 2 24-bit DACs. The maximum supported + sampling rate is 192 kHz. + + It is connected internally to one out of a selection of the internal I2S + controllers. + + The RK3308 audio codec has 8 independent capture channels, but some + features work on stereo pairs called groups: + * grp 0 -- MIC1 / MIC2 + * grp 1 -- MIC3 / MIC4 + * grp 2 -- MIC5 / MIC6 + * grp 3 -- MIC7 / MIC8 + +maintainers: + - Luca Ceresoli <luca.ceresoli@xxxxxxxxxxx> + +properties: + compatible: + const: rockchip,rk3308-codec + + reg: + maxItems: 1 + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the General Register Files (GRF) + + clocks: + items: + - description: clock for TX + - description: clock for RX + - description: AHB clock driving the interface + + clock-names: + items: + - const: mclk_tx + - const: mclk_rx + - const: hclk + + resets: true + + reset-names: + items: + - const: "acodec" + + "#sound-dai-cells": + const: 0 + + rockchip,micbias-avdd-multiplier: + description: | + Voltage setting for the MICBIAS pins expressed as a multiplier of + AVDD. + + E.g. if rockchip,micbias-avdd-multiplier = 7 (x0.85) and AVDD = 3v3, + then MIC BIAS voltage will be 3.3 V * 0.85 = 2.805 V. + + Value 0: multiplier = 0.50 + Value N: multiplier = 0.50 + 0.05 * N + Value 7: multiplier = 0.85 + + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 7 + +required: + - compatible + - reg + - rockchip,grf + - clocks + - resets + - "#sound-dai-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3308-cru.h> + + acodec: acodec@ff560000 { + compatible = "rockchip,rk3308-codec"; + reg = <0xff560000 0x10000>; + rockchip,grf = <&grf>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + clocks = <&cru SCLK_I2S2_8CH_TX_OUT>, + <&cru SCLK_I2S2_8CH_RX_OUT>, + <&cru PCLK_ACODEC>; + reset-names = "acodec"; + resets = <&cru SRST_ACODEC_P>; + #sound-dai-cells = <0>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 895e8ace80dd..d53a8e74cb1e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17588,6 +17588,12 @@ S: Maintained F: Documentation/devicetree/bindings/media/rockchip-rga.yaml F: drivers/media/platform/rockchip/rga/ +ROCKCHIP RK3308 INTERNAL AUDIO CODEC +M: Luca Ceresoli <luca.ceresoli@xxxxxxxxxxx> +S: Maintained +F: Documentation/devicetree/bindings/sound/rockchip,rk3308-codec.yaml +F: include/dt-bindings/sound/rockchip,rk3308-codec.h + ROCKCHIP VIDEO DECODER DRIVER M: Ezequiel Garcia <ezequiel@xxxxxxxxxxxxxxxxxxxx> L: linux-media@xxxxxxxxxxxxxxx diff --git a/include/dt-bindings/sound/rockchip,rk3308-codec.h b/include/dt-bindings/sound/rockchip,rk3308-codec.h new file mode 100644 index 000000000000..9f1b210a048e --- /dev/null +++ b/include/dt-bindings/sound/rockchip,rk3308-codec.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __DT_BINDINGS_ROCKCHIP_RK3308_CODEC_H__ +#define __DT_BINDINGS_ROCKCHIP_RK3308_CODEC_H__ + +#define RK3308_CODEC_MICBIAS_AVDD_x_0_50 0 +#define RK3308_CODEC_MICBIAS_AVDD_x_0_55 1 +#define RK3308_CODEC_MICBIAS_AVDD_x_0_60 2 +#define RK3308_CODEC_MICBIAS_AVDD_x_0_65 3 +#define RK3308_CODEC_MICBIAS_AVDD_x_0_70 4 +#define RK3308_CODEC_MICBIAS_AVDD_x_0_75 5 +#define RK3308_CODEC_MICBIAS_AVDD_x_0_80 6 +#define RK3308_CODEC_MICBIAS_AVDD_x_0_85 7 +#define RK3308_CODEC_MICBIAS_NUM 8 + +#endif /* __DT_BINDINGS_ROCKCHIP_RK3308_CODEC_H__ */ -- 2.34.1
