Reset soundwire block on frame sync generation clock reset.
Without this we are hitting read/write timeouts randomly during
runtime pm. Along with this remove a swr_reset redundant flag.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
---
sound/soc/codecs/lpass-tx-macro.c | 15 ++++-----------
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c
index 55503ba480bb..c19bb19b717b 100644
--- a/sound/soc/codecs/lpass-tx-macro.c
+++ b/sound/soc/codecs/lpass-tx-macro.c
@@ -268,7 +268,6 @@ struct tx_macro {
struct clk *fsgen;
struct clk_hw hw;
bool dec_active[NUM_DECIMATORS];
- bool reset_swr;
int tx_mclk_users;
u16 dmic_clk_div;
bool bcs_enable;
@@ -1702,18 +1701,14 @@ static int swclk_gate_enable(struct clk_hw *hw)
}
tx_macro_mclk_enable(tx, true);
- if (tx->reset_swr)
- regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
- CDC_TX_SWR_RESET_MASK,
- CDC_TX_SWR_RESET_ENABLE);
+ regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
+ CDC_TX_SWR_RESET_MASK, CDC_TX_SWR_RESET_ENABLE);
regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
CDC_TX_SWR_CLK_EN_MASK,
CDC_TX_SWR_CLK_ENABLE);
- if (tx->reset_swr)
- regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
- CDC_TX_SWR_RESET_MASK, 0x0);
- tx->reset_swr = false;
+ regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
+ CDC_TX_SWR_RESET_MASK, 0x0);
return 0;
}
@@ -1855,7 +1850,6 @@ static int tx_macro_probe(struct platform_device *pdev)
dev_set_drvdata(dev, tx);
- tx->reset_swr = true;
tx->dev = dev;
/* set MCLK and NPL rates */
@@ -1970,7 +1964,6 @@ static int __maybe_unused tx_macro_runtime_resume(struct device *dev)
regcache_cache_only(tx->regmap, false);
regcache_sync(tx->regmap);
- tx->reset_swr = true;
return 0;
err_fsgen:
--
2.21.0
