Hi Matt, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on broonie-sound/for-next] [also build test WARNING on tiwai-sound/for-next linus/master v5.19 next-20220808] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Matt-Flax/ASoC-codecs-add-support-for-the-TI-SRC4392-codec/20220808-152201 base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next config: riscv-randconfig-r042-20220808 (https://download.01.org/0day-ci/archive/20220809/202208090035.KZkaKxvw-lkp@xxxxxxxxx/config) compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 5f1c7e2cc5a3c07cbc2412e851a7283c1841f520) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install riscv cross compiling tool for clang build # apt-get install binutils-riscv64-linux-gnu # https://github.com/intel-lab-lkp/linux/commit/34effe739961486f8c9451714111ee6ad4df8dbd git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Matt-Flax/ASoC-codecs-add-support-for-the-TI-SRC4392-codec/20220808-152201 git checkout 34effe739961486f8c9451714111ee6ad4df8dbd # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash sound/soc/codecs/ If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot <lkp@xxxxxxxxx> All warnings (new ones prefixed by >>): >> sound/soc/codecs/src4xxx.c:292:3: warning: variable 'd' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ sound/soc/codecs/src4xxx.c:309:59: note: uninitialized use occurs here ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_11, d); ^ sound/soc/codecs/src4xxx.c:235:20: note: initialize the variable 'd' to silence this warning int val, pj, jd, d; ^ = 0 >> sound/soc/codecs/src4xxx.c:292:3: warning: variable 'jd' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ sound/soc/codecs/src4xxx.c:304:59: note: uninitialized use occurs here ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_10, jd); ^~ sound/soc/codecs/src4xxx.c:235:17: note: initialize the variable 'jd' to silence this warning int val, pj, jd, d; ^ = 0 >> sound/soc/codecs/src4xxx.c:292:3: warning: variable 'pj' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ sound/soc/codecs/src4xxx.c:299:59: note: uninitialized use occurs here ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_0F, pj); ^~ sound/soc/codecs/src4xxx.c:235:13: note: initialize the variable 'pj' to silence this warning int val, pj, jd, d; ^ = 0 3 warnings generated. vim +/d +292 sound/soc/codecs/src4xxx.c 227 228 static int src4xxx_hw_params(struct snd_pcm_substream *substream, 229 struct snd_pcm_hw_params *params, 230 struct snd_soc_dai *dai) 231 { 232 struct snd_soc_component *component = dai->component; 233 struct src4xxx *src4xxx = snd_soc_component_get_drvdata(component); 234 unsigned int mclk_div; 235 int val, pj, jd, d; 236 int reg = SRC4XXX_PORTA_CTL_04; 237 int ret; 238 239 if (dai->id == SRC4XXX_PORTB) 240 reg = SRC4XXX_PORTB_CTL_06; 241 242 dev_info(dai->dev, "__func__ enter for dai %d\n", dai->id); 243 244 if (src4xxx->master[dai->id]) { 245 mclk_div = src4xxx->mclk_hz/params_rate(params); 246 if (src4xxx->mclk_hz != mclk_div*params_rate(params)) { 247 dev_err(component->dev, 248 "mclk %d / rate %d has a remainder.\n", 249 src4xxx->mclk_hz, params_rate(params)); 250 return -EINVAL; 251 } 252 253 dev_info(dai->dev, "__func__ mclk %d rate %d div %d\n", 254 src4xxx->mclk_hz, params_rate(params), mclk_div); 255 val = ((int)mclk_div - 128) / 128; 256 dev_info(dai->dev, 257 "__func__ register value = %d\n", val); 258 if ((val < 0) | (val > 3)) { 259 dev_err(component->dev, 260 "div register setting %d is out of range\n", 261 val); 262 dev_err(component->dev, 263 "unsupported sample rate %d Hz for the master clock of %d Hz\n", 264 params_rate(params), src4xxx->mclk_hz); 265 return -EINVAL; 266 } 267 268 /* set the TX DIV */ 269 ret = regmap_update_bits(src4xxx->regmap, 270 SRC4XXX_TX_CTL_07, SRC4XXX_TX_MCLK_DIV_MASK, 271 val<<SRC4XXX_TX_MCLK_DIV_SHIFT); 272 if (ret) { 273 dev_err(component->dev, 274 "Couldn't set the TX's div register to %d << %d = 0x%x\n", 275 val, SRC4XXX_TX_MCLK_DIV_SHIFT, 276 val<<SRC4XXX_TX_MCLK_DIV_SHIFT); 277 return ret; 278 } 279 280 /* set the PLL for the digital receiver */ 281 switch (src4xxx->mclk_hz) { 282 case 24576000: 283 pj = 0x22; 284 jd = 0x00; 285 d = 0x00; 286 break; 287 case 22579200: 288 pj = 0x22; 289 jd = 0x1b; 290 d = 0xa3; 291 break; > 292 default: 293 /* don't error out here, 294 * other parts of the chip are still functional 295 */ 296 dev_info(component->dev, 297 "Couldn't set the RCV PLL as this master clock rate is unknown\n"); 298 } 299 ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_0F, pj); 300 if (ret < 0) 301 dev_err(component->dev, 302 "Failed to update PLL register 0x%x\n", 303 SRC4XXX_RCV_PLL_0F); 304 ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_10, jd); 305 if (ret < 0) 306 dev_err(component->dev, 307 "Failed to update PLL register 0x%x\n", 308 SRC4XXX_RCV_PLL_10); 309 ret = regmap_write(src4xxx->regmap, SRC4XXX_RCV_PLL_11, d); 310 if (ret < 0) 311 dev_err(component->dev, 312 "Failed to update PLL register 0x%x\n", 313 SRC4XXX_RCV_PLL_11); 314 315 ret = regmap_update_bits(src4xxx->regmap, 316 SRC4XXX_TX_CTL_07, SRC4XXX_TX_MCLK_DIV_MASK, 317 val<<SRC4XXX_TX_MCLK_DIV_SHIFT); 318 if (ret < 0) { 319 dev_err(component->dev, 320 "Couldn't set the TX's div register to %d << %d = 0x%x\n", 321 val, SRC4XXX_TX_MCLK_DIV_SHIFT, 322 val<<SRC4XXX_TX_MCLK_DIV_SHIFT); 323 return ret; 324 } 325 326 return regmap_update_bits(src4xxx->regmap, reg, 327 SRC4XXX_MCLK_DIV_MASK, val); 328 } else 329 dev_info(dai->dev, "not setting up MCLK as not master\n"); 330 331 return 0; 332 }; 333 -- 0-DAY CI Kernel Test Service https://01.org/lkp
