On Sat, Aug 06, 2022 at 12:21:20AM +0200, Niklas Carlsson wrote: > + * Steps for performing the reset: > + * 1) Make sure that the cache is marked as dirty by writing all > + * default values directly to the cache. Why? If there's some need to mark the cache as dirty there's a function that directly does that. Note especially that a cache sync will explicitly not write any default values to the hardware if it knows about them. > + * 2) Enable the core clock which is needed for writing all registers > + * except CLOCK_CONTROL. > + * > + * 3) Use regcache_sync() for synchronizing the dirty cache back to > + * the hardware. We then need to disable clock control at the end (which the code does but the comment doesn't). It might be better to just have comments next to the individual steps here. I'd expect something more like enable clock for each register except CLOCK_CONTROL write the default disable clock here, no faffing with the cache. You could use two bulk writes to do the writes of registers below and above CLOCK_CONTROL if that's the goal in doing a cache sync.
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