On 2022/6/3 下午 06:10, Mark Brown wrote:
On Fri, Jun 03, 2022 at 05:55:18PM +0800, Hui Wang wrote:
On 6/2/22 18:33, Mark Brown wrote:
Thanks for your comment. But it is weird, it doesn't work like you said,
probably need specific route setting in the machine driver level?
Is this triggering due to reprogramming the PLL for one direction
while the other is already active (eg, starting a capture during
a playba
Yes, it is. With the current machine driver of fsl-asoc-card.c, if starting
a capture during a playback or starting a playback during a capture, the
codec driver will reprogram PLL parameters while PLL is on.
So your patch fixes that case - note however that you're probably
getting an audio glitch in the already active stream while doing
this. I'll send a patch which should improve that shortly. BTW,
shouldn't the PLL power be left off if the output frequency is 0?
Agree Mark's comment.
By the way, when the platform's dai_link support be_hw_params_fixup
callback, the sample rate will be fixed to same rate, so PLL will not be
also reconfigured during playback and recording at the same time.
And in another case, if the snd_soc_dai_set_pll() is called in the
card->set_bias_level() instead of card_hw_params(), the PLL will keep being
off since check_mclk_select_pll() always returns false.
That should be fixable...
