On Wed, 2022-05-04 at 15:38 -0500, Rob Herring wrote: > On Fri, Apr 29, 2022 at 04:30:37PM -0400, Nícolas F. R. A. Prado > wrote: > > The Mediatek AFE PCM controller for MT8192 allows sharing of an I2S > > bus > > between two busses. Add a pattern for these properties in the > > dt-binding. > > > > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx> > > > > --- > > > > Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml | 5 > > +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe- > > pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe- > > pcm.yaml > > index 7a25bc9b8060..5b03c8dbf318 100644 > > --- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml > > +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml > > @@ -54,6 +54,11 @@ properties: > > - const: aud_infra_clk > > - const: aud_infra_26m_clk > > > > +patternProperties: > > + "^i2s[0-35-9]-share$": > > + description: Name of the I2S bus that is shared with this bus > > + pattern: "^I2S[0-35-9]$" > > Why not a phandle to the the other bus? That would be the DT way to > do > it. But I'm not sure I really understand who is sharing what here. > I can explain the usage of this property. The I2S interface of MT8192 only have 3 pins [bit clock/ frame clock/ data in(or out)]. So if we want use them as normal I2S that has 4 pins [bit clock/ frame clock/ data in/ data out], we need to combine two MT8192 I2S interface to use. But we need to specify whose clock they use. E.g. "i2s9-share = "I2S8"". > > + > > required: > > - compatible > > - interrupts > > -- > > 2.36.0 > > > >
