This patch adds mt8186 hostless dai driver.
Signed-off-by: Jiaxin Yu <jiaxin.yu@xxxxxxxxxxxx>
---
.../soc/mediatek/mt8186/mt8186-dai-hostless.c | 295 ++++++++++++++++++
1 file changed, 295 insertions(+)
create mode 100644 sound/soc/mediatek/mt8186/mt8186-dai-hostless.c
diff --git a/sound/soc/mediatek/mt8186/mt8186-dai-hostless.c b/sound/soc/mediatek/mt8186/mt8186-dai-hostless.c
new file mode 100644
index 000000000000..37460a3acc93
--- /dev/null
+++ b/sound/soc/mediatek/mt8186/mt8186-dai-hostless.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// MediaTek ALSA SoC Audio DAI Hostless Control
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Jiaxin Yu <jiaxin.yu@xxxxxxxxxxxx>
+
+#include "mt8186-afe-common.h"
+
+static const struct snd_pcm_hardware mt8186_hostless_hardware = {
+ .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_MMAP_VALID),
+ .period_bytes_min = 256,
+ .period_bytes_max = 4 * 48 * 1024,
+ .periods_min = 2,
+ .periods_max = 256,
+ .buffer_bytes_max = 4 * 48 * 1024,
+ .fifo_size = 0,
+};
+
+/* dai component */
+static const struct snd_soc_dapm_route mtk_dai_hostless_routes[] = {
+ /* Hostless ADDA Loopback */
+ {"ADDA_DL_CH1", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
+ {"ADDA_DL_CH1", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
+ {"ADDA_DL_CH2", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
+ {"ADDA_DL_CH2", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
+ {"I2S1_CH1", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
+ {"I2S1_CH2", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
+ {"I2S3_CH1", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
+ {"I2S3_CH1", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
+ {"I2S3_CH2", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
+ {"I2S3_CH2", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
+ {"Hostless LPBK UL", NULL, "ADDA_UL_Mux"},
+
+ /* Hostelss FM */
+ /* connsys_i2s to hw gain 1*/
+ {"Hostless FM UL", NULL, "Connsys I2S"},
+
+ {"HW_GAIN1_IN_CH1", "CONNSYS_I2S_CH1 Switch", "Hostless FM DL"},
+ {"HW_GAIN1_IN_CH2", "CONNSYS_I2S_CH2 Switch", "Hostless FM DL"},
+ /* hw gain to adda dl */
+ {"Hostless FM UL", NULL, "HW Gain 1 Out"},
+
+ {"ADDA_DL_CH1", "GAIN1_OUT_CH1 Switch", "Hostless FM DL"},
+ {"ADDA_DL_CH2", "GAIN1_OUT_CH2 Switch", "Hostless FM DL"},
+ /* hw gain to i2s3 */
+ {"I2S3_CH1", "GAIN1_OUT_CH1 Switch", "Hostless FM DL"},
+ {"I2S3_CH2", "GAIN1_OUT_CH2 Switch", "Hostless FM DL"},
+ /* hw gain to i2s1 */
+ {"I2S1_CH1", "GAIN1_OUT_CH1 Switch", "Hostless FM DL"},
+ {"I2S1_CH2", "GAIN1_OUT_CH2 Switch", "Hostless FM DL"},
+
+ /* Hostless_SRC */
+ {"ADDA_DL_CH1", "SRC_1_OUT_CH1 Switch", "Hostless_SRC_1_DL"},
+ {"ADDA_DL_CH2", "SRC_1_OUT_CH2 Switch", "Hostless_SRC_1_DL"},
+ {"I2S1_CH1", "SRC_1_OUT_CH1 Switch", "Hostless_SRC_1_DL"},
+ {"I2S1_CH2", "SRC_1_OUT_CH2 Switch", "Hostless_SRC_1_DL"},
+ {"I2S3_CH1", "SRC_1_OUT_CH1 Switch", "Hostless_SRC_1_DL"},
+ {"I2S3_CH2", "SRC_1_OUT_CH2 Switch", "Hostless_SRC_1_DL"},
+ {"Hostless_SRC_1_UL", NULL, "HW_SRC_1_Out"},
+
+ /* Hostless_SRC_bargein */
+ {"HW_SRC_1_IN_CH1", "I2S0_CH1 Switch", "Hostless_SRC_Bargein_DL"},
+ {"HW_SRC_1_IN_CH2", "I2S0_CH2 Switch", "Hostless_SRC_Bargein_DL"},
+ {"Hostless_SRC_Bargein_UL", NULL, "I2S0"},
+
+ /* Hostless AAudio */
+ {"Hostless HW Gain AAudio In", NULL, "HW Gain 2 In"},
+ {"Hostless SRC AAudio UL", NULL, "HW Gain 2 Out"},
+ {"HW_SRC_2_IN_CH1", "HW_GAIN2_OUT_CH1 Switch", "Hostless SRC AAudio DL"},
+ {"HW_SRC_2_IN_CH2", "HW_GAIN2_OUT_CH2 Switch", "Hostless SRC AAudio DL"},
+};
+
+/* dai ops */
+static int mtk_dai_hostless_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ int ret;
+
+ snd_soc_set_runtime_hwparams(substream, &mt8186_hostless_hardware);
+
+ ret = snd_pcm_hw_constraint_integer(runtime,
+ SNDRV_PCM_HW_PARAM_PERIODS);
+ if (ret < 0)
+ dev_info(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
