On Fri, Apr 18, 2008 at 11:13 AM, Daniel Mack <daniel@xxxxxxxxx> wrote: > Hi Jarkko, > > No, the 256-clock mode is for output only, while in my setup the TLV is > in slave mode. I attached this chip to the I2S output of an PXA270 which > always outputs sample rate * 256 as system clock. In this very case, the > PLL can be bypassed by selecting the left path described on page 27. > Ok, now I see. Probably you should refer it as, at least in comment, 128*Q instead of 256 eventhough the driver is not currently touching the Q value in AIC3X_PLL_PROGA_REG. > AIC3X_SAMPLE_RATE_SEL_REG defaults to 0 which is what I want in this > case. Thus, I don't have to write it. > > Are you sure this is a general case? Jarkko _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
