On Thu, 2022-01-06 at 12:26 +0000, Mark Brown wrote:
> On Wed, Jan 05, 2022 at 04:51:43PM -0600, Robert Hancock wrote:
>
> > struct clk *axi_clk;
> > + unsigned int last_sysclk;
>
> Typically this would just be called sysclk - calling it last_sysclk
> makes things a bit confusing. It's being used as though it were the
> current sysclk and that's what set_sysclk() is supposed to be for.
Will switch to just sysclk.
>
> > + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
> > + adata->last_sysclk) {
> > + unsigned int mclk_fs = DIV_ROUND_CLOSEST(adata->last_sysclk,
> > params_rate(params));
> > +
> > + writel(mclk_fs, stream_data->mmio + XLNX_AUD_FS_MULTIPLIER);
> > + }
> > +
>
> Does the IP actually cope properly with inexact ratios, especially if
> the actual clock rate is lower than mclk_fs would suggest? It's more
> common to be able to tolerate a higher clock than specified.
Unknown at this point - the test setup I have has a fixed sample rate so I
can't really test it. The documentation is unclear on exactly why this register
exists and what it's used for, it just indicates it should be set for the
sample rate to MCLK multiplier. All I really know for sure is that with it left
set to the default of 384 when the actual multiplier is 256, it doesn't work
properly.
>
> It's interesting that this is only for playback.
--
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
www.calian.com
