DSP Audio Ports bindings have been documented with DSP services bindings
which makes it difficult to reuse them, so pull them out in to a dedicated
bindings.
Also as part of this change convert them into yaml format.
This patch also removes q6afe bindings as dsp services are now documented in
apr bindings.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
---
.../devicetree/bindings/sound/qcom,q6afe.txt | 201 -----------------
.../sound/qcom,q6dsp-audio-ports.yaml | 177 +++++++++++++++
include/dt-bindings/sound/qcom,q6afe.h | 204 +----------------
.../sound/qcom,q6dsp-audio-ports.h | 208 ++++++++++++++++++
4 files changed, 387 insertions(+), 403 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/qcom,q6afe.txt
create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-audio-ports.yaml
create mode 100644 include/dt-bindings/sound/qcom,q6dsp-audio-ports.h
diff --git a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt
deleted file mode 100644
index 2d6fb2ea75a0..000000000000
--- a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt
+++ /dev/null
@@ -1,201 +0,0 @@
-Qualcomm Audio Front End (Q6AFE) binding
-
-AFE is one of the APR audio service on Q6DSP
-Please refer to qcom,apr.txt for details of the common apr service bindings
-used by all apr services. Must contain the following properties.
-
-- compatible:
- Usage: required
- Value type: <stringlist>
- Definition: must be "qcom,q6afe-v<MAJOR-NUMBER>.<MINOR-NUMBER>"
- Or "qcom,q6afe" where the version number can be queried
- from DSP.
- example "qcom,q6afe"
-
-= AFE DAIs (Digial Audio Interface)
-"dais" subnode of the AFE node. It represents afe dais, each afe dai is a
-subnode of "dais" representing board specific dai setup.
-"dais" node should have following properties followed by dai children.
-
-- compatible:
- Usage: required
- Value type: <stringlist>
- Definition: must be "qcom,q6afe-dais"
-
-- #sound-dai-cells
- Usage: required
- Value type: <u32>
- Definition: Must be 1
-
-- #address-cells
- Usage: required
- Value type: <u32>
- Definition: Must be 1
-
-- #size-cells
- Usage: required
- Value type: <u32>
- Definition: Must be 0
-
-== AFE DAI is subnode of "dais" and represent a dai, it includes board specific
-configuration of each dai. Must contain the following properties.
-
-- reg
- Usage: required
- Value type: <u32>
- Definition: Must be dai id
-
-- qcom,sd-lines
- Usage: required for mi2s interface
- Value type: <prop-encoded-array>
- Definition: Must be list of serial data lines used by this dai.
- should be one or more of the 0-3 sd lines.
-
- - qcom,tdm-sync-mode:
- Usage: required for tdm interface
- Value type: <prop-encoded-array>
- Definition: Synchronization mode.
- 0 - Short sync bit mode
- 1 - Long sync mode
- 2 - Short sync slot mode
-
- - qcom,tdm-sync-src:
- Usage: required for tdm interface
- Value type: <prop-encoded-array>
- Definition: Synchronization source.
- 0 - External source
- 1 - Internal source
-
- - qcom,tdm-data-out:
- Usage: required for tdm interface
- Value type: <prop-encoded-array>
- Definition: Data out signal to drive with other masters.
- 0 - Disable
- 1 - Enable
-
- - qcom,tdm-invert-sync:
- Usage: required for tdm interface
- Value type: <prop-encoded-array>
- Definition: Invert the sync.
- 0 - Normal
- 1 - Invert
-
- - qcom,tdm-data-delay:
- Usage: required for tdm interface
- Value type: <prop-encoded-array>
- Definition: Number of bit clock to delay data
- with respect to sync edge.
- 0 - 0 bit clock cycle
- 1 - 1 bit clock cycle
- 2 - 2 bit clock cycle
-
- - qcom,tdm-data-align:
- Usage: required for tdm interface
- Value type: <prop-encoded-array>
- Definition: Indicate how data is packed
- within the slot. For example, 32 slot width in case of
- sample bit width is 24.
- 0 - MSB
- 1 - LSB
-
-= AFE CLOCKSS
-"clocks" subnode of the AFE node. It represents q6afe clocks
-"clocks" node should have following properties.
-- compatible:
- Usage: required
- Value type: <stringlist>
- Definition: must be "qcom,q6afe-clocks"
-
-- #clock-cells:
- Usage: required
- Value type: <u32>
- Definition: Must be 2. Clock Id followed by
- below valid clock coupling attributes.
- 1 - for no coupled clock
- 2 - for dividend of the coupled clock
- 3 - for divisor of the coupled clock
- 4 - for inverted and no couple clock
-
-= EXAMPLE
-
-apr-service@4 {
- compatible = "qcom,q6afe";
- reg = <APR_SVC_AFE>;
-
- dais {
- compatible = "qcom,q6afe-dais";
- #sound-dai-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- dai@1 {
- reg = <HDMI_RX>;
- };
-
- dai@24 {
- reg = <PRIMARY_TDM_RX_0>;
- qcom,tdm-sync-mode = <1>:
- qcom,tdm-sync-src = <1>;
- qcom,tdm-data-out = <0>;
- qcom,tdm-invert-sync = <1>;
- qcom,tdm-data-delay = <1>;
- qcom,tdm-data-align = <0>;
-
- };
-
- dai@25 {
- reg = <PRIMARY_TDM_TX_0>;
- qcom,tdm-sync-mode = <1>:
- qcom,tdm-sync-src = <1>;
- qcom,tdm-data-out = <0>;
- qcom,tdm-invert-sync = <1>;
- qcom,tdm-data-delay <1>:
- qcom,tdm-data-align = <0>;
- };
-
- dai@16 {
- reg = <PRIMARY_MI2S_RX>;
- qcom,sd-lines = <0 2>;
- };
-
- dai@17 {
- reg = <PRIMARY_MI2S_TX>;
- qcom,sd-lines = <1>;
- };
-
- dai@18 {
- reg = <SECONDARY_MI2S_RX>;
- qcom,sd-lines = <0 3>;
- };
-
- dai@19 {
- reg = <SECONDARY_MI2S_TX>;
- qcom,sd-lines = <1>;
- };
-
- dai@20 {
- reg = <TERTIARY_MI2S_RX>;
- qcom,sd-lines = <1 3>;
- };
-
- dai@21 {
- reg = <TERTIARY_MI2S_TX>;
- qcom,sd-lines = <0>;
- };
-
- dai@22 {
- reg = <QUATERNARY_MI2S_RX>;
- qcom,sd-lines = <0>;
- };
-
- dai@23 {
- reg = <QUATERNARY_MI2S_TX>;
- qcom,sd-lines = <1>;
- };
- };
-
- clocks {
- compatible = "qcom,q6afe-clocks";
- #clock-cells = <2>;
- };
-};
diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-audio-ports.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-audio-ports.yaml
new file mode 100644
index 000000000000..6990295803a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-audio-ports.yaml
@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/sound/qcom,q6dsp-audio-ports.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Qualcomm DSP Audio Ports binding
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
+
+description: |
+ This binding describes the Qualcomm DSP Audio ports
+
+properties:
+ compatible:
+ const: qcom,q6afe-dais
+
+ reg:
+ maxItems: 1
+
+ '#sound-dai-cells':
+ const: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+#Digital Audio Interfaces
+patternProperties:
+ '^dai@[0-9]+$':
+ type: object
+ description:
+ Q6DSP Digital Audio Interfaces.
+
+ properties:
+ reg:
+ description:
+ Digital Audio Interface ID
+
+ qcom,sd-lines:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ List of serial data lines used by this dai.should be one or more of the 0-3 sd lines.
+ minItems: 1
+ maxItems: 4
+ uniqueItems: true
+ items:
+ minimum: 0
+ maximum: 3
+
+ qcom,tdm-sync-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+ description:
+ TDM Synchronization mode
+ 0 = Short sync bit mode
+ 1 = Long sync mode
+ 2 = Short sync slot mode
+
+ qcom,tdm-sync-src:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ description:
+ TDM Synchronization source
+ 0 = External source
+ 1 = Internal source
+
+ qcom,tdm-data-out:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ description:
+ TDM Data out signal to drive with other masters
+ 0 = Disable
+ 1 = Enable
+
+ qcom,tdm-invert-sync:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ description:
+ TDM Invert the sync
+ 0 = Normal
+ 1 = Invert
+
+ qcom,tdm-data-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+ description:
+ TDM Number of bit clock to delay data
+ 0 = 0 bit clock cycle
+ 1 = 1 bit clock cycle
+ 2 = 2 bit clock cycle
+
+ qcom,tdm-data-align:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+ description:
+ Indicate how data is packed within the slot. For example, 32 slot
+ width in case of sample bit width is 24TDM Invert the sync.
+ 0 = MSB
+ 1 = LSB
+
+ required:
+ - reg
+
+ allOf:
+ - if:
+ properties:
+ reg:
+ contains:
+ # TDM DAI ID range from PRIMARY_TDM_RX_0 - QUINARY_TDM_TX_7
+ items:
+ minimum: 24
+ maximum: 103
+ then:
+ required:
+ - qcom,tdm-sync-mode
+ - qcom,tdm-sync-src
+ - qcom,tdm-data-out
+ - qcom,tdm-invert-sync
+ - qcom,tdm-data-delay
+ - qcom,tdm-data-align
+
+ - if:
+ properties:
+ reg:
+ contains:
+ # MI2S DAI ID range PRIMARY_MI2S_RX - QUATERNARY_MI2S_TX and
+ # QUINARY_MI2S_RX - QUINARY_MI2S_TX
+ items:
+ oneOf:
+ - minimum: 16
+ maximum: 23
+ - minimum: 127
+ maximum: 128
+ then:
+ required:
+ - qcom,sd-lines
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#sound-dai-cells"
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/soc/qcom,apr.h>
+ #include <dt-bindings/sound/qcom,q6afe.h>
+ apr {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ apr-service@4 {
+ reg = <APR_SVC_AFE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ q6afedai@1 {
+ compatible = "qcom,q6afe-dais";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+
+ dai@22 {
+ reg = <QUATERNARY_MI2S_RX>;
+ qcom,sd-lines = <0 1 2 3>;
+ };
+ };
+ };
+ };
diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h
index 66c21ab03eef..d4cf293e2b8f 100644
--- a/include/dt-bindings/sound/qcom,q6afe.h
+++ b/include/dt-bindings/sound/qcom,q6afe.h
@@ -2,207 +2,7 @@
#ifndef __DT_BINDINGS_Q6_AFE_H__
#define __DT_BINDINGS_Q6_AFE_H__
-/* Audio Front End (AFE) virtual ports IDs */
-#define HDMI_RX 1
-#define SLIMBUS_0_RX 2
-#define SLIMBUS_0_TX 3
-#define SLIMBUS_1_RX 4
-#define SLIMBUS_1_TX 5
-#define SLIMBUS_2_RX 6
-#define SLIMBUS_2_TX 7
-#define SLIMBUS_3_RX 8
-#define SLIMBUS_3_TX 9
-#define SLIMBUS_4_RX 10
-#define SLIMBUS_4_TX 11
-#define SLIMBUS_5_RX 12
-#define SLIMBUS_5_TX 13
-#define SLIMBUS_6_RX 14
-#define SLIMBUS_6_TX 15
-#define PRIMARY_MI2S_RX 16
-#define PRIMARY_MI2S_TX 17
-#define SECONDARY_MI2S_RX 18
-#define SECONDARY_MI2S_TX 19
-#define TERTIARY_MI2S_RX 20
-#define TERTIARY_MI2S_TX 21
-#define QUATERNARY_MI2S_RX 22
-#define QUATERNARY_MI2S_TX 23
-#define PRIMARY_TDM_RX_0 24
-#define PRIMARY_TDM_TX_0 25
-#define PRIMARY_TDM_RX_1 26
-#define PRIMARY_TDM_TX_1 27
-#define PRIMARY_TDM_RX_2 28
-#define PRIMARY_TDM_TX_2 29
-#define PRIMARY_TDM_RX_3 30
-#define PRIMARY_TDM_TX_3 31
-#define PRIMARY_TDM_RX_4 32
-#define PRIMARY_TDM_TX_4 33
-#define PRIMARY_TDM_RX_5 34
-#define PRIMARY_TDM_TX_5 35
-#define PRIMARY_TDM_RX_6 36
-#define PRIMARY_TDM_TX_6 37
-#define PRIMARY_TDM_RX_7 38
-#define PRIMARY_TDM_TX_7 39
-#define SECONDARY_TDM_RX_0 40
-#define SECONDARY_TDM_TX_0 41
-#define SECONDARY_TDM_RX_1 42
-#define SECONDARY_TDM_TX_1 43
-#define SECONDARY_TDM_RX_2 44
-#define SECONDARY_TDM_TX_2 45
-#define SECONDARY_TDM_RX_3 46
-#define SECONDARY_TDM_TX_3 47
-#define SECONDARY_TDM_RX_4 48
-#define SECONDARY_TDM_TX_4 49
-#define SECONDARY_TDM_RX_5 50
-#define SECONDARY_TDM_TX_5 51
-#define SECONDARY_TDM_RX_6 52
-#define SECONDARY_TDM_TX_6 53
-#define SECONDARY_TDM_RX_7 54
-#define SECONDARY_TDM_TX_7 55
-#define TERTIARY_TDM_RX_0 56
-#define TERTIARY_TDM_TX_0 57
-#define TERTIARY_TDM_RX_1 58
-#define TERTIARY_TDM_TX_1 59
-#define TERTIARY_TDM_RX_2 60
-#define TERTIARY_TDM_TX_2 61
-#define TERTIARY_TDM_RX_3 62
-#define TERTIARY_TDM_TX_3 63
-#define TERTIARY_TDM_RX_4 64
-#define TERTIARY_TDM_TX_4 65
-#define TERTIARY_TDM_RX_5 66
-#define TERTIARY_TDM_TX_5 67
-#define TERTIARY_TDM_RX_6 68
-#define TERTIARY_TDM_TX_6 69
-#define TERTIARY_TDM_RX_7 70
-#define TERTIARY_TDM_TX_7 71
-#define QUATERNARY_TDM_RX_0 72
-#define QUATERNARY_TDM_TX_0 73
-#define QUATERNARY_TDM_RX_1 74
-#define QUATERNARY_TDM_TX_1 75
-#define QUATERNARY_TDM_RX_2 76
-#define QUATERNARY_TDM_TX_2 77
-#define QUATERNARY_TDM_RX_3 78
-#define QUATERNARY_TDM_TX_3 79
-#define QUATERNARY_TDM_RX_4 80
-#define QUATERNARY_TDM_TX_4 81
-#define QUATERNARY_TDM_RX_5 82
-#define QUATERNARY_TDM_TX_5 83
-#define QUATERNARY_TDM_RX_6 84
-#define QUATERNARY_TDM_TX_6 85
-#define QUATERNARY_TDM_RX_7 86
-#define QUATERNARY_TDM_TX_7 87
-#define QUINARY_TDM_RX_0 88
-#define QUINARY_TDM_TX_0 89
-#define QUINARY_TDM_RX_1 90
-#define QUINARY_TDM_TX_1 91
-#define QUINARY_TDM_RX_2 92
-#define QUINARY_TDM_TX_2 93
-#define QUINARY_TDM_RX_3 94
-#define QUINARY_TDM_TX_3 95
-#define QUINARY_TDM_RX_4 96
-#define QUINARY_TDM_TX_4 97
-#define QUINARY_TDM_RX_5 98
-#define QUINARY_TDM_TX_5 99
-#define QUINARY_TDM_RX_6 100
-#define QUINARY_TDM_TX_6 101
-#define QUINARY_TDM_RX_7 102
-#define QUINARY_TDM_TX_7 103
-#define DISPLAY_PORT_RX 104
-#define WSA_CODEC_DMA_RX_0 105
-#define WSA_CODEC_DMA_TX_0 106
-#define WSA_CODEC_DMA_RX_1 107
-#define WSA_CODEC_DMA_TX_1 108
-#define WSA_CODEC_DMA_TX_2 109
-#define VA_CODEC_DMA_TX_0 110
-#define VA_CODEC_DMA_TX_1 111
-#define VA_CODEC_DMA_TX_2 112
-#define RX_CODEC_DMA_RX_0 113
-#define TX_CODEC_DMA_TX_0 114
-#define RX_CODEC_DMA_RX_1 115
-#define TX_CODEC_DMA_TX_1 116
-#define RX_CODEC_DMA_RX_2 117
-#define TX_CODEC_DMA_TX_2 118
-#define RX_CODEC_DMA_RX_3 119
-#define TX_CODEC_DMA_TX_3 120
-#define RX_CODEC_DMA_RX_4 121
-#define TX_CODEC_DMA_TX_4 122
-#define RX_CODEC_DMA_RX_5 123
-#define TX_CODEC_DMA_TX_5 124
-#define RX_CODEC_DMA_RX_6 125
-#define RX_CODEC_DMA_RX_7 126
-#define QUINARY_MI2S_RX 127
-#define QUINARY_MI2S_TX 128
-
-#define LPASS_CLK_ID_PRI_MI2S_IBIT 1
-#define LPASS_CLK_ID_PRI_MI2S_EBIT 2
-#define LPASS_CLK_ID_SEC_MI2S_IBIT 3
-#define LPASS_CLK_ID_SEC_MI2S_EBIT 4
-#define LPASS_CLK_ID_TER_MI2S_IBIT 5
-#define LPASS_CLK_ID_TER_MI2S_EBIT 6
-#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7
-#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8
-#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9
-#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10
-#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11
-#define LPASS_CLK_ID_QUI_MI2S_IBIT 12
-#define LPASS_CLK_ID_QUI_MI2S_EBIT 13
-#define LPASS_CLK_ID_SEN_MI2S_IBIT 14
-#define LPASS_CLK_ID_SEN_MI2S_EBIT 15
-#define LPASS_CLK_ID_INT0_MI2S_IBIT 16
-#define LPASS_CLK_ID_INT1_MI2S_IBIT 17
-#define LPASS_CLK_ID_INT2_MI2S_IBIT 18
-#define LPASS_CLK_ID_INT3_MI2S_IBIT 19
-#define LPASS_CLK_ID_INT4_MI2S_IBIT 20
-#define LPASS_CLK_ID_INT5_MI2S_IBIT 21
-#define LPASS_CLK_ID_INT6_MI2S_IBIT 22
-#define LPASS_CLK_ID_QUI_MI2S_OSR 23
-#define LPASS_CLK_ID_PRI_PCM_IBIT 24
-#define LPASS_CLK_ID_PRI_PCM_EBIT 25
-#define LPASS_CLK_ID_SEC_PCM_IBIT 26
-#define LPASS_CLK_ID_SEC_PCM_EBIT 27
-#define LPASS_CLK_ID_TER_PCM_IBIT 28
-#define LPASS_CLK_ID_TER_PCM_EBIT 29
-#define LPASS_CLK_ID_QUAD_PCM_IBIT 30
-#define LPASS_CLK_ID_QUAD_PCM_EBIT 31
-#define LPASS_CLK_ID_QUIN_PCM_IBIT 32
-#define LPASS_CLK_ID_QUIN_PCM_EBIT 33
-#define LPASS_CLK_ID_QUI_PCM_OSR 34
-#define LPASS_CLK_ID_PRI_TDM_IBIT 35
-#define LPASS_CLK_ID_PRI_TDM_EBIT 36
-#define LPASS_CLK_ID_SEC_TDM_IBIT 37
-#define LPASS_CLK_ID_SEC_TDM_EBIT 38
-#define LPASS_CLK_ID_TER_TDM_IBIT 39
-#define LPASS_CLK_ID_TER_TDM_EBIT 40
-#define LPASS_CLK_ID_QUAD_TDM_IBIT 41
-#define LPASS_CLK_ID_QUAD_TDM_EBIT 42
-#define LPASS_CLK_ID_QUIN_TDM_IBIT 43
-#define LPASS_CLK_ID_QUIN_TDM_EBIT 44
-#define LPASS_CLK_ID_QUIN_TDM_OSR 45
-#define LPASS_CLK_ID_MCLK_1 46
-#define LPASS_CLK_ID_MCLK_2 47
-#define LPASS_CLK_ID_MCLK_3 48
-#define LPASS_CLK_ID_MCLK_4 49
-#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50
-#define LPASS_CLK_ID_INT_MCLK_0 51
-#define LPASS_CLK_ID_INT_MCLK_1 52
-#define LPASS_CLK_ID_MCLK_5 53
-#define LPASS_CLK_ID_WSA_CORE_MCLK 54
-#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55
-#define LPASS_CLK_ID_VA_CORE_MCLK 56
-#define LPASS_CLK_ID_TX_CORE_MCLK 57
-#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58
-#define LPASS_CLK_ID_RX_CORE_MCLK 59
-#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60
-#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61
-
-#define LPASS_HW_AVTIMER_VOTE 101
-#define LPASS_HW_MACRO_VOTE 102
-#define LPASS_HW_DCODEC_VOTE 103
-
-#define Q6AFE_MAX_CLK_ID 104
-
-#define LPASS_CLK_ATTRIBUTE_INVALID 0x0
-#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1
-#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2
-#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3
+/* This file exists due to backward compatibility reasons, Please do not DELETE! */
+#include <dt-bindings/sound/qcom,q6dsp-audio-ports.h>
#endif /* __DT_BINDINGS_Q6_AFE_H__ */
diff --git a/include/dt-bindings/sound/qcom,q6dsp-audio-ports.h b/include/dt-bindings/sound/qcom,q6dsp-audio-ports.h
new file mode 100644
index 000000000000..cb242183ff1f
--- /dev/null
+++ b/include/dt-bindings/sound/qcom,q6dsp-audio-ports.h
@@ -0,0 +1,208 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_Q6DSP_AUDIO_PORTS_H__
+#define __DT_BINDINGS_Q6DSP_AUDIO_PORTS_H__
+
+/* Audio Front End (AFE) virtual ports IDs */
+#define HDMI_RX 1
+#define SLIMBUS_0_RX 2
+#define SLIMBUS_0_TX 3
+#define SLIMBUS_1_RX 4
+#define SLIMBUS_1_TX 5
+#define SLIMBUS_2_RX 6
+#define SLIMBUS_2_TX 7
+#define SLIMBUS_3_RX 8
+#define SLIMBUS_3_TX 9
+#define SLIMBUS_4_RX 10
+#define SLIMBUS_4_TX 11
+#define SLIMBUS_5_RX 12
+#define SLIMBUS_5_TX 13
+#define SLIMBUS_6_RX 14
+#define SLIMBUS_6_TX 15
+#define PRIMARY_MI2S_RX 16
+#define PRIMARY_MI2S_TX 17
+#define SECONDARY_MI2S_RX 18
+#define SECONDARY_MI2S_TX 19
+#define TERTIARY_MI2S_RX 20
+#define TERTIARY_MI2S_TX 21
+#define QUATERNARY_MI2S_RX 22
+#define QUATERNARY_MI2S_TX 23
+#define PRIMARY_TDM_RX_0 24
+#define PRIMARY_TDM_TX_0 25
+#define PRIMARY_TDM_RX_1 26
+#define PRIMARY_TDM_TX_1 27
+#define PRIMARY_TDM_RX_2 28
+#define PRIMARY_TDM_TX_2 29
+#define PRIMARY_TDM_RX_3 30
+#define PRIMARY_TDM_TX_3 31
+#define PRIMARY_TDM_RX_4 32
+#define PRIMARY_TDM_TX_4 33
+#define PRIMARY_TDM_RX_5 34
+#define PRIMARY_TDM_TX_5 35
+#define PRIMARY_TDM_RX_6 36
+#define PRIMARY_TDM_TX_6 37
+#define PRIMARY_TDM_RX_7 38
+#define PRIMARY_TDM_TX_7 39
+#define SECONDARY_TDM_RX_0 40
+#define SECONDARY_TDM_TX_0 41
+#define SECONDARY_TDM_RX_1 42
+#define SECONDARY_TDM_TX_1 43
+#define SECONDARY_TDM_RX_2 44
+#define SECONDARY_TDM_TX_2 45
+#define SECONDARY_TDM_RX_3 46
+#define SECONDARY_TDM_TX_3 47
+#define SECONDARY_TDM_RX_4 48
+#define SECONDARY_TDM_TX_4 49
+#define SECONDARY_TDM_RX_5 50
+#define SECONDARY_TDM_TX_5 51
+#define SECONDARY_TDM_RX_6 52
+#define SECONDARY_TDM_TX_6 53
+#define SECONDARY_TDM_RX_7 54
+#define SECONDARY_TDM_TX_7 55
+#define TERTIARY_TDM_RX_0 56
+#define TERTIARY_TDM_TX_0 57
+#define TERTIARY_TDM_RX_1 58
+#define TERTIARY_TDM_TX_1 59
+#define TERTIARY_TDM_RX_2 60
+#define TERTIARY_TDM_TX_2 61
+#define TERTIARY_TDM_RX_3 62
+#define TERTIARY_TDM_TX_3 63
+#define TERTIARY_TDM_RX_4 64
+#define TERTIARY_TDM_TX_4 65
+#define TERTIARY_TDM_RX_5 66
+#define TERTIARY_TDM_TX_5 67
+#define TERTIARY_TDM_RX_6 68
+#define TERTIARY_TDM_TX_6 69
+#define TERTIARY_TDM_RX_7 70
+#define TERTIARY_TDM_TX_7 71
+#define QUATERNARY_TDM_RX_0 72
+#define QUATERNARY_TDM_TX_0 73
+#define QUATERNARY_TDM_RX_1 74
+#define QUATERNARY_TDM_TX_1 75
+#define QUATERNARY_TDM_RX_2 76
+#define QUATERNARY_TDM_TX_2 77
+#define QUATERNARY_TDM_RX_3 78
+#define QUATERNARY_TDM_TX_3 79
+#define QUATERNARY_TDM_RX_4 80
+#define QUATERNARY_TDM_TX_4 81
+#define QUATERNARY_TDM_RX_5 82
+#define QUATERNARY_TDM_TX_5 83
+#define QUATERNARY_TDM_RX_6 84
+#define QUATERNARY_TDM_TX_6 85
+#define QUATERNARY_TDM_RX_7 86
+#define QUATERNARY_TDM_TX_7 87
+#define QUINARY_TDM_RX_0 88
+#define QUINARY_TDM_TX_0 89
+#define QUINARY_TDM_RX_1 90
+#define QUINARY_TDM_TX_1 91
+#define QUINARY_TDM_RX_2 92
+#define QUINARY_TDM_TX_2 93
+#define QUINARY_TDM_RX_3 94
+#define QUINARY_TDM_TX_3 95
+#define QUINARY_TDM_RX_4 96
+#define QUINARY_TDM_TX_4 97
+#define QUINARY_TDM_RX_5 98
+#define QUINARY_TDM_TX_5 99
+#define QUINARY_TDM_RX_6 100
+#define QUINARY_TDM_TX_6 101
+#define QUINARY_TDM_RX_7 102
+#define QUINARY_TDM_TX_7 103
+#define DISPLAY_PORT_RX 104
+#define WSA_CODEC_DMA_RX_0 105
+#define WSA_CODEC_DMA_TX_0 106
+#define WSA_CODEC_DMA_RX_1 107
+#define WSA_CODEC_DMA_TX_1 108
+#define WSA_CODEC_DMA_TX_2 109
+#define VA_CODEC_DMA_TX_0 110
+#define VA_CODEC_DMA_TX_1 111
+#define VA_CODEC_DMA_TX_2 112
+#define RX_CODEC_DMA_RX_0 113
+#define TX_CODEC_DMA_TX_0 114
+#define RX_CODEC_DMA_RX_1 115
+#define TX_CODEC_DMA_TX_1 116
+#define RX_CODEC_DMA_RX_2 117
+#define TX_CODEC_DMA_TX_2 118
+#define RX_CODEC_DMA_RX_3 119
+#define TX_CODEC_DMA_TX_3 120
+#define RX_CODEC_DMA_RX_4 121
+#define TX_CODEC_DMA_TX_4 122
+#define RX_CODEC_DMA_RX_5 123
+#define TX_CODEC_DMA_TX_5 124
+#define RX_CODEC_DMA_RX_6 125
+#define RX_CODEC_DMA_RX_7 126
+#define QUINARY_MI2S_RX 127
+#define QUINARY_MI2S_TX 128
+
+#define LPASS_CLK_ID_PRI_MI2S_IBIT 1
+#define LPASS_CLK_ID_PRI_MI2S_EBIT 2
+#define LPASS_CLK_ID_SEC_MI2S_IBIT 3
+#define LPASS_CLK_ID_SEC_MI2S_EBIT 4
+#define LPASS_CLK_ID_TER_MI2S_IBIT 5
+#define LPASS_CLK_ID_TER_MI2S_EBIT 6
+#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7
+#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8
+#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9
+#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10
+#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11
+#define LPASS_CLK_ID_QUI_MI2S_IBIT 12
+#define LPASS_CLK_ID_QUI_MI2S_EBIT 13
+#define LPASS_CLK_ID_SEN_MI2S_IBIT 14
+#define LPASS_CLK_ID_SEN_MI2S_EBIT 15
+#define LPASS_CLK_ID_INT0_MI2S_IBIT 16
+#define LPASS_CLK_ID_INT1_MI2S_IBIT 17
+#define LPASS_CLK_ID_INT2_MI2S_IBIT 18
+#define LPASS_CLK_ID_INT3_MI2S_IBIT 19
+#define LPASS_CLK_ID_INT4_MI2S_IBIT 20
+#define LPASS_CLK_ID_INT5_MI2S_IBIT 21
+#define LPASS_CLK_ID_INT6_MI2S_IBIT 22
+#define LPASS_CLK_ID_QUI_MI2S_OSR 23
+#define LPASS_CLK_ID_PRI_PCM_IBIT 24
+#define LPASS_CLK_ID_PRI_PCM_EBIT 25
+#define LPASS_CLK_ID_SEC_PCM_IBIT 26
+#define LPASS_CLK_ID_SEC_PCM_EBIT 27
+#define LPASS_CLK_ID_TER_PCM_IBIT 28
+#define LPASS_CLK_ID_TER_PCM_EBIT 29
+#define LPASS_CLK_ID_QUAD_PCM_IBIT 30
+#define LPASS_CLK_ID_QUAD_PCM_EBIT 31
+#define LPASS_CLK_ID_QUIN_PCM_IBIT 32
+#define LPASS_CLK_ID_QUIN_PCM_EBIT 33
+#define LPASS_CLK_ID_QUI_PCM_OSR 34
+#define LPASS_CLK_ID_PRI_TDM_IBIT 35
+#define LPASS_CLK_ID_PRI_TDM_EBIT 36
+#define LPASS_CLK_ID_SEC_TDM_IBIT 37
+#define LPASS_CLK_ID_SEC_TDM_EBIT 38
+#define LPASS_CLK_ID_TER_TDM_IBIT 39
+#define LPASS_CLK_ID_TER_TDM_EBIT 40
+#define LPASS_CLK_ID_QUAD_TDM_IBIT 41
+#define LPASS_CLK_ID_QUAD_TDM_EBIT 42
+#define LPASS_CLK_ID_QUIN_TDM_IBIT 43
+#define LPASS_CLK_ID_QUIN_TDM_EBIT 44
+#define LPASS_CLK_ID_QUIN_TDM_OSR 45
+#define LPASS_CLK_ID_MCLK_1 46
+#define LPASS_CLK_ID_MCLK_2 47
+#define LPASS_CLK_ID_MCLK_3 48
+#define LPASS_CLK_ID_MCLK_4 49
+#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50
+#define LPASS_CLK_ID_INT_MCLK_0 51
+#define LPASS_CLK_ID_INT_MCLK_1 52
+#define LPASS_CLK_ID_MCLK_5 53
+#define LPASS_CLK_ID_WSA_CORE_MCLK 54
+#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55
+#define LPASS_CLK_ID_VA_CORE_MCLK 56
+#define LPASS_CLK_ID_TX_CORE_MCLK 57
+#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58
+#define LPASS_CLK_ID_RX_CORE_MCLK 59
+#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60
+#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61
+
+#define LPASS_HW_AVTIMER_VOTE 101
+#define LPASS_HW_MACRO_VOTE 102
+#define LPASS_HW_DCODEC_VOTE 103
+
+#define Q6AFE_MAX_CLK_ID 104
+
+#define LPASS_CLK_ATTRIBUTE_INVALID 0x0
+#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1
+#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2
+#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3
+
+#endif /* __DT_BINDINGS_Q6DSP_AUDIO_PORTS_H__ */
--
2.21.0
