On 14-07-21, 13:13, Bard Liao wrote: > From: Pierre-Louis Bossart <pierre-louis.bossart@xxxxxxxxxxxxxxx> > > The Cadence IP exposes a small number of self-clearing bits in > the MCP_CONTROL and MCP_CONFIG_UPDATE registers. > > We currently do not check that those bits are indeed cleared, > e.g. during resume operations. That could lead to resuming peripheral > devices too early. > > In addition, if we happen to read these registers, update one of the > fields and write the register back, we may be writing stale data that > might have been cleared in hardware. These sort of race conditions > could lead to e.g. doing a hw_reset twice or stopping a clock that > just restarted. There is no clear way of avoiding these potential race > conditions other than making sure that these registers fields are > cleared before any read-modify-write sequence. If we detect this sort > of errors, we only log them since there is no clear recovery > possible. The only way out is likely to restart the IP with a > suspend/resume cycle. > > Note that the checks are performed before updating the registers, as > well as after the Intel 'sync go' sequence in multi-link mode. That > should cover both the start and end of suspend/resume hardware > configurations. The Multi-Master mode gates the configuration updates > until the 'sync go' signal is asserted, so we only check on init and > after the end of the 'sync go' sequence. > > The duration of the usleep_range() was defined by the GSYNC frequency > used in multi-master mode. With a 4kHz frequency, any configuration > change might be deferred by up to 250us. Extending the range to > 1000-1500us should guarantee that the configuration change is > completed without any significant impact on the overall resume > time. There were some checkpatch warns, but I think code will looks worse if we split lines up, so applied now -- ~Vinod
