On 6/7/21 11:28 AM, Lu, Brent wrote:
This also looks like we have two topologies configuring the same DAIs
differently on different platforms.
Why can't we pick one configuration that would work in all cases?
The comment just say we are reusing rt5685's sof-jsl-rt5682-mx98360a.tplg.
This patch does not care about the dai sequence. Maybe I should reword
the commit log.
I was referring to the bclk frequency, one case uses 2.4 and the other
3.072MHz.
The 2.4MHz setting isn't ready when we enabled this codec so we selected
3.072MHz. Since we are updating topology for PLL issue soon, we can change
bclk frequency to 2.4MHz as well. How do you think?
The 3.072MHz clock will require the 24.576MHz PLL to be on on the
SOC/PCH. If you can use 2.4 MHz without any loss of quality and the
codec can deal with 25 bit slots with 24-bit data it's better power-wise.
We try to use 64.fs only when it's absolutely mandatory, e.g. if the
codec or amplifier doesn't support the 25/24 configuration. IIRC this
was the case with TI PCM512x and Maxim amps.
We've also used the 3.072 MHz bit clock when there are constraints on
the clock sources and selectors. This isn't the case on GLK but the SOF
commit 0a97c1a92f2d93bd4d45bc99d61e362cd214748c clarified the clock
selection for newer platforms, including JSL. In the end we may be
forced to use the 3.072 MHz PLL, you'd need to look at the various
topologies used with this machine driver.
