On Fri, Apr 23, 2021 at 09:54:38PM +0530, Vijendar Mukunda wrote: > For CZ/StoneyRidge platforms, ACP DMA between ACP SRAM and > I2S FIFO should be stopped before stopping I2S Controller DMA. > When DMA is progressing and stop request received, while DMA transfer > ongoing between ACP SRAM and I2S FIFO, Stopping I2S DMA prior to ACP DMA > stop resulting DMA Channel stop failure. This again... copying in Peter for the sequencing discussion. If we need to do this I'm not convinced that bodging it in the driver is a good idea, and especially not deferring it outside of the trigger operation - for example on a suspend or pause we won't actually do a shutdown() so the trigger will end up not happening which seems like it may cause problems. We'd probably be better off with the core knowing what's going on and being able to reorder the callbacks although designing an interface for that seems a bit annoying. > This issue can't be fixed in ACP DMA driver due to design constraint. What is the design constraint here - can't we fix the design? Or is it a hardware design constraint (presumably broken signalling between the I2S and DMA blocks)?
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