On Thu, Mar 18, 2021 at 10:24:30AM -0500, Chris Morgan wrote: > On Thu, Mar 18, 2021 at 01:06:10PM +0000, Mark Brown wrote: > > This should really validate freq_in and freq_out, confirming that > > they're whatever fixed values this register sequence is for (if you > > don't know what freq_out actually is it's more OK to skip that than > > freq_in I guess since the constraints on the DAI link should ensure we > > end up with a sensible value). > Unfortunately I don't know which values I should validate. While the data > sheet has these fields "documented" it doesn't have the units, so I don't know > if I'm close in the minimum/maximum range or not. I will add documentation to > the routine for each step of what I'm doing at least though. If better > documentation becomes available or a second implementation presents itself we > can update this to validate. > https://rockchip.fr/RK817%20datasheet%20V1.01.pdf I see... for freq_in and freq_out you shouldn't need to understand any of the actual PLL configuration, only what goes in and/or comes out of it which isn't super clear from the datasheet - there's no clock tree or anything. It does say the input clock is "main clk" so it could be the MCLK pin? The only other plausible pin I'm seeing is the 32kHz clock. If you know the output clock then PLL_OUTDIV will tell you the operating frequency of the PLL. BTW looking at the driver there's a bunch of other registers so shouldn't the regmap be done at the MFD level?
Attachment:
signature.asc
Description: PGP signature
