On Tue, Mar 16, 2021 at 02:53:45PM -0500, Chris Morgan wrote:
> +static int rk817_init(struct snd_soc_component *component)
> +{
> + struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
> +
> + snd_soc_component_write(component, RK817_CODEC_APLL_CFG1, 0x58);
> + snd_soc_component_write(component, RK817_CODEC_APLL_CFG2, 0x2d);
> + snd_soc_component_write(component, RK817_CODEC_APLL_CFG3, 0x0c);
> + snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5);
These should be pushed into a set_pll() call, even if it just accepts
only fixed arguments.
> + snd_soc_component_write(component, RK817_CODEC_DMIC_PGA_GAIN, 0x99);
This looks like it should be a user visible gain control.
> + snd_soc_component_init_regmap(component, rk817->regmap);
> + rk817->component = component;
> +
> + clk_prepare_enable(rk817->mclk);
Should check the return value of clk_prepare_enable().
> +
> + clk_prepare_enable(rk817_codec_data->mclk);
> +
> + ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk817,
The driver is enabling the clock in both component and device level
probes - I'd just leave it in the device level probe only if you're not
actively managing it. You'd need to add a remove() function with the
matching disable.
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