Hello Viorel Suman,
The patch 28564486866f: "ASoC: fsl_xcvr: Add XCVR ASoC CPU DAI
driver" from Oct 13, 2020, leads to the following static checker
warning:
sound/soc/fsl/fsl_xcvr.c:393 fsl_xcvr_en_aud_pll()
warn: 'xcvr->phy_clk' not released on lines: 373.
sound/soc/fsl/fsl_xcvr.c
351 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
352 {
353 struct device *dev = &xcvr->pdev->dev;
354 int ret;
355
356 clk_disable_unprepare(xcvr->phy_clk);
357 ret = clk_set_rate(xcvr->phy_clk, freq);
358 if (ret < 0) {
359 dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret);
360 return ret;
361 }
362 ret = clk_prepare_enable(xcvr->phy_clk);
363 if (ret) {
364 dev_err(dev, "failed to start PHY clock: %d\n", ret);
365 return ret;
366 }
367
368 /* Release AI interface from reset */
369 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
370 FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
371 if (ret < 0) {
372 dev_err(dev, "Error while setting IER0: %d\n", ret);
clck_disable_unprepare(xcvr->phy_clk)?
373 return ret;
374 }
375
376 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
377 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
378 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
379 FSL_XCVR_PHY_CTRL_TSDIFF_OE |
380 FSL_XCVR_PHY_CTRL_PHY_EN, 1);
381 /* PHY: CTRL2_SET: EARC_TX_MODE */
382 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
383 FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
384 } else { /* SPDIF mode */
385 /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */
386 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
387 FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS |
388 FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
389 }
390
391 dev_dbg(dev, "PLL Fexp: %u\n", freq);
392
393 return 0;
394 }
regards,
dan carpenter
