On Wed, Oct 21, 2020 at 04:53:53PM +0800, Jiaxin Yu wrote: > This patch adds mt8192 audio afe document. > > This patch depends on following series that has not been accepted: > https://patchwork.kernel.org/cover/11752231 > (dt-bindings/clock/mt8192-clk.h is included in it.) > https://patchwork.kernel.org/patch/11755895 > (dt-bindings/power/mt8192-power.h is included in it.) > https://lore.kernel.org/patchwork/patch/1321118 > (dt-bindings/reset-controller/mt8192-resets.h is included in it.) > > Signed-off-by: Jiaxin Yu <jiaxin.yu@xxxxxxxxxxxx> > --- > .../bindings/sound/mt8192-afe-pcm.yaml | 103 ++++++++++++++++++ > 1 file changed, 103 insertions(+) > create mode 100644 Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml > > diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml > new file mode 100644 > index 0000000000000..7c2f07b8b66dd > --- /dev/null > +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml > @@ -0,0 +1,103 @@ > +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/sound/mt8192-afe-pcm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek AFE PCM controller for mt8192 > + > +maintainers: > + - Jiaxin Yu <jiaxin.yu@xxxxxxxxxxxx> > + - Shane Chien <shane.chien@xxxxxxxxxxxx> > + > +properties: > + compatible: > + const: mediatek,mt8192-audio > + > + interrupts: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + reset-names: > + const: audiosys > + > + mediatek,apmixedsys: > + $ref: "/schemas/types.yaml#/definitions/phandle" > + maxItems: 1 A 'phandle' is already 1 item. Drop 'maxItems'. > + description: The phandle of the mediatek apmixedsys controller > + > + mediatek,infracfg: > + $ref: "/schemas/types.yaml#/definitions/phandle" > + maxItems: 1 > + description: The phandle of the mediatek infracfg controller > + > + mediatek,topckgen: > + $ref: "/schemas/types.yaml#/definitions/phandle" > + maxItems: 1 > + description: The phandle of the mediatek topckgen controller > + > + power-domains: > + maxItems: 1 > + > + clocks: > + items: > + - description: AFE clock > + - description: ADDA DAC clock > + - description: ADDA DAC pre-distortion clock > + - description: audio infra sys clock > + - description: audio infra 26M clock > + > + clock-names: > + items: > + - const: aud_afe_clk > + - const: aud_dac_clk > + - const: aud_dac_predis_clk > + - const: aud_infra_clk > + - const: aud_infra_26m_clk > + > +required: > + - compatible > + - interrupts > + - resets > + - reset-names > + - mediatek,apmixedsys > + - mediatek,infracfg > + - mediatek,topckgen > + - power-domains > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt8192-clk.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/power/mt8192-power.h> > + #include <dt-bindings/reset-controller/mt8192-resets.h> > + > + afe: mt8192-afe-pcm { > + compatible = "mediatek,mt8192-audio"; > + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; > + resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>; > + reset-names = "audiosys"; > + mediatek,apmixedsys = <&apmixedsys>; > + mediatek,infracfg = <&infracfg>; > + mediatek,topckgen = <&topckgen>; > + power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>; > + clocks = <&audsys CLK_AUD_AFE>, > + <&audsys CLK_AUD_DAC>, > + <&audsys CLK_AUD_DAC_PREDIS>, > + <&infracfg CLK_INFRA_AUDIO>, > + <&infracfg CLK_INFRA_AUDIO_26M_B>; > + clock-names = "aud_afe_clk", > + "aud_dac_clk", > + "aud_dac_predis_clk", > + "aud_infra_clk", > + "aud_infra_26m_clk"; > + }; > + > +... > -- > 2.18.0
