On Wed, Oct 14, 2020 at 01:19:34AM -0500, Samuel Holland wrote: > The sun8i codec has three clock/sample rate domains: > - The AIF1 domain, with a sample rate equal to AIF1 LRCK > - The AIF2 domain, with a sample rate equal to AIF2 LRCK > - The SYSCLK domain, containing the ADC, DAC, and effects (AGC/DRC), > with a sample rate given by a divisor from SYSCLK. The divisor is > controlled by the AIF1_FS or AIF2_FS field in SYS_SR_CTRL, depending > on if SYSCLK's source is AIF1CLK or AIF2CLK, respectively. The exact > sample rate depends on if SYSCLK is running at 22.6 MHz or 24.6 MHz. > > When an AIF (currently only AIF1) is active, the ADC and DAC should run > at that sample rate to avoid artifacting. Sample rate conversion is only > available when multiple AIFs are active and are routed to each other; > this means the sample rate conversion hardware usually cannot be used. > > Only attach the event hook to the channel 0 AIF widgets, since we only > need one event when a DAI stream starts or stops. Channel 0 is always > brought up with a DAI stream, regardless of the number of channels in > the stream. > > The ADC and DAC (along with their effects blocks) can be used even if > no AIFs are in use. In that case, we should select an appropriate sample > rate divisor, instead of keeping the last-used AIF sample rate. > 44.1/48 kHz was chosen to balance audio quality and power consumption. > > Since the sample rate is tied to active AIF paths, disabling pmdown_time > allows switching to the optimal sample rate immediately, instead of > after a 5 second delay. > > Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx> Acked-by: Maxime Ripard <mripard@xxxxxxxxxx> Thanks! Maxime
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