j721e or j7200 SOM can be attached to the same Common Processor Board (CPB)
With the j7200 SOM only the 48KHz family parent clock is available and
McASP0 is used for the audio.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@xxxxxx>
---
.../bindings/sound/ti,j721e-cpb-audio.yaml | 92 ++++++++++++++-----
1 file changed, 70 insertions(+), 22 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/ti,j721e-cpb-audio.yaml b/Documentation/devicetree/bindings/sound/ti,j721e-cpb-audio.yaml
index d52cfbeb2d07..805da4d6a88e 100644
--- a/Documentation/devicetree/bindings/sound/ti,j721e-cpb-audio.yaml
+++ b/Documentation/devicetree/bindings/sound/ti,j721e-cpb-audio.yaml
@@ -18,18 +18,25 @@ description: |
PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
different HSDIVIDER.
- Clocking setup for 48KHz family:
- PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
- |-> PLL4_HSDIV2 ---> AUDIO_REFCLK2 ---> pcm3168a.SCKI
+ Clocking setup for j721e:
+ 48KHz family:
+ PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
+ |-> PLL4_HSDIV2 ---> AUDIO_REFCLK2 ---> pcm3168a.SCKI
- Clocking setup for 44.1KHz family:
- PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
- |-> PLL15_HSDIV2 ---> AUDIO_REFCLK2 ---> pcm3168a.SCKI
+ 44.1KHz family:
+ PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
+ |-> PLL15_HSDIV2 ---> AUDIO_REFCLK2 ---> pcm3168a.SCKI
+
+ Clocking setup for j7200:
+ 48KHz family:
+ PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
+ |-> PLL4_HSDIV2 ---> AUDIO_REFCLK2 ---> pcm3168a.SCKI
properties:
compatible:
- items:
- - const: ti,j721e-cpb-audio
+ enum:
+ - ti,j721e-cpb-audio
+ - ti,j7200-cpb-audio
model:
$ref: /schemas/types.yaml#/definitions/string
@@ -44,22 +51,12 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle
clocks:
- items:
- - description: AUXCLK clock for McASP used by CPB audio
- - description: Parent for CPB_McASP auxclk (for 48KHz)
- - description: Parent for CPB_McASP auxclk (for 44.1KHz)
- - description: SCKI clock for the pcm3168a codec on CPB
- - description: Parent for CPB_SCKI clock (for 48KHz)
- - description: Parent for CPB_SCKI clock (for 44.1KHz)
+ minItems: 4
+ maxItems: 6
clock-names:
- items:
- - const: cpb-mcasp-auxclk
- - const: cpb-mcasp-auxclk-48000
- - const: cpb-mcasp-auxclk-44100
- - const: cpb-codec-scki
- - const: cpb-codec-scki-48000
- - const: cpb-codec-scki-44100
+ minItems: 4
+ maxItems: 6
required:
- compatible
@@ -71,6 +68,57 @@ required:
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,j721e-cpb-audio
+
+ then:
+ properties:
+ clocks:
+ minItems: 6
+ items:
+ - description: AUXCLK clock for McASP used by CPB audio
+ - description: Parent for CPB_McASP auxclk (for 48KHz)
+ - description: Parent for CPB_McASP auxclk (for 44.1KHz)
+ - description: SCKI clock for the pcm3168a codec on CPB
+ - description: Parent for CPB_SCKI clock (for 48KHz)
+ - description: Parent for CPB_SCKI clock (for 44.1KHz)
+
+ clock-names:
+ items:
+ - const: cpb-mcasp-auxclk
+ - const: cpb-mcasp-auxclk-48000
+ - const: cpb-mcasp-auxclk-44100
+ - const: cpb-codec-scki
+ - const: cpb-codec-scki-48000
+ - const: cpb-codec-scki-44100
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,j7200-cpb-audio
+
+ then:
+ properties:
+ clocks:
+ maxItems: 4
+ items:
+ - description: AUXCLK clock for McASP used by CPB audio
+ - description: Parent for CPB_McASP auxclk (for 48KHz)
+ - description: SCKI clock for the pcm3168a codec on CPB
+ - description: Parent for CPB_SCKI clock (for 48KHz)
+
+ clock-names:
+ items:
+ - const: cpb-mcasp-auxclk
+ - const: cpb-mcasp-auxclk-48000
+ - const: cpb-codec-scki
+ - const: cpb-codec-scki-48000
+
examples:
- |+
sound {
--
Peter
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
