To avoid the actual PLL settings to differ from the state expected by
the clock driver, the codec should only be fully reset before the clocks
are registered. But we also need to ensure that the software reset
happens at all before clock registration, as not all boards have a reset
GPIO.
Move the software reset from aic32x4_component_probe() to
aic32x4_probe() and reorder the reset and registration sequence:
1. Reset via GPIO (if available)
2. Reset via software
3. Register component
4. Register clocks
Note that aic32x4_component_probe() is only called after aic32x4_probe()
has finished, so the reset in aic32x4_component_probe() was happening too
late.
Signed-off-by: Matthias Schiffer <matthias.schiffer@xxxxxxxxxxxxxxx>
---
sound/soc/codecs/tlv320aic32x4.c | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c
index a45fb496082c..470dc0ef0359 100644
--- a/sound/soc/codecs/tlv320aic32x4.c
+++ b/sound/soc/codecs/tlv320aic32x4.c
@@ -981,8 +981,6 @@ static int aic32x4_component_probe(struct snd_soc_component *component)
if (ret)
return ret;
- snd_soc_component_write(component, AIC32X4_RESET, 0x01);
-
if (aic32x4->setup)
aic32x4_setup_gpios(component);
@@ -1226,6 +1224,16 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap)
return ret;
}
+ if (gpio_is_valid(aic32x4->rstn_gpio)) {
+ ndelay(10);
+ gpio_set_value_cansleep(aic32x4->rstn_gpio, 1);
+ mdelay(1);
+ }
+
+ ret = regmap_write(regmap, AIC32X4_RESET, 0x01);
+ if (ret)
+ goto err_disable_regulators;
+
ret = devm_snd_soc_register_component(dev,
&soc_component_dev_aic32x4, &aic32x4_dai, 1);
if (ret) {
@@ -1233,12 +1241,6 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap)
goto err_disable_regulators;
}
- if (gpio_is_valid(aic32x4->rstn_gpio)) {
- ndelay(10);
- gpio_set_value_cansleep(aic32x4->rstn_gpio, 1);
- mdelay(1);
- }
-
ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
if (ret)
goto err_disable_regulators;
--
2.17.1
