On Wed, Jul 15, 2020 at 06:18:38PM +0200, Arnaud Ferraris wrote: > Hi, > > Le 15/07/2020 à 16:05, Mark Brown a écrit : > > On Tue, Jul 14, 2020 at 01:50:50PM -0700, Nicolin Chen wrote: > > Anything wrong with ASRC selecting SSI1 clock for both cases? The > > driver calculates the divisors based on the given clock rate, so > > the final internal rate should be the same. If there's a problem, > > I feel that's a separate bug. > > Calculations are indeed good, but then the clock selection setting in > the ASRCSR register would also use SSI1 as the input clock, which > doesn't work in our case. Could you please elaborate why it doesn't work?
