On Fri, Apr 24, 2020 at 10:01:38AM +0800, Shengjiu Wang wrote: > Previously CLOCKING2 is set as a volatile register, but cause > issue at suspend & resume, that some bits of CLOCKING2 is not > restored at resume, for example SYSCLK_SRC bits, then the output > clock is wrong. > > The volatile property is caused by CLASSD_CLK_DIV bits, > which are controlled by the chip itself. But the datasheet > claims these are read only and protected by the security key, > and they are not read by the driver at all. > > So it should be safe to change CLOCKING2 to be non-volatile. > > Signed-off-by: Shengjiu Wang <shengjiu.wang@xxxxxxx> > --- Acked-by: Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx> Thanks, Charles
