On Tue, Apr 21, 2020 at 08:02:15PM +0800, Shengjiu Wang wrote:
> The CLOCKING2 is a volatile register, but some bits should
> be restored when resume, for example SYSCLK_SRC. otherwise
> the output clock is wrong
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@xxxxxxx>
> ---
> sound/soc/codecs/wm8962.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c
> index d9d59f45833f..6e96c0c5ad2a 100644
> --- a/sound/soc/codecs/wm8962.c
> +++ b/sound/soc/codecs/wm8962.c
> @@ -82,6 +82,7 @@ struct wm8962_priv {
> #endif
>
> int irq;
> + u32 regcache_clocking2;
> };
>
> /* We can't use the same notifier block for more than one supply and
> @@ -3813,6 +3814,10 @@ static int wm8962_runtime_resume(struct device *dev)
>
> regcache_sync(wm8962->regmap);
>
> + regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
> + WM8962_SYSCLK_SRC_MASK,
> + wm8962->regcache_clocking2);
> +
I wonder if it might just be better to make the register
non-volatile? From looking through the datasheet I am guessing
this is volatile for the CLASSD_CLK_DIV bits, which are
controlled by the chip itself. But the datasheet claims these are
read only and protected by the security key, and they are not
read by the driver at all.
Thanks,
Charles
> regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
> WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
> WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
> @@ -3842,6 +3847,9 @@ static int wm8962_runtime_suspend(struct device *dev)
> WM8962_STARTUP_BIAS_ENA |
> WM8962_VMID_BUF_ENA, 0);
>
> + regmap_read(wm8962->regmap, WM8962_CLOCKING2,
> + &wm8962->regcache_clocking2);
> +
> regcache_cache_only(wm8962->regmap, true);
>
> regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
> --
> 2.21.0
>
