On Mon, Apr 20, 2020 at 02:56:31PM +0200, Clément Péron wrote: > On Mon, 20 Apr 2020 at 14:44, Maxime Ripard <maxime@xxxxxxxxxx> wrote: > > > > On Sun, Apr 19, 2020 at 12:44:32AM +0200, Clément Péron wrote: > > > From: Marcus Cooper <codekipper@xxxxxxxxx> > > > > > > On the newer SoCs such as the H3 and A64 this is set by default > > > to transfer a 0 after each sample in each slot. However the A10 > > > and A20 SoCs that this driver was developed on had a default > > > setting where it padded the audio gain with zeros. > > > > > > This isn't a problem whilst we have only support for 16bit audio > > > but with larger sample resolution rates in the pipeline then SEXT > > > bits should be cleared so that they also pad at the LSB. Without > > > this the audio gets distorted. > > > > > > Signed-off-by: Marcus Cooper <codekipper@xxxxxxxxx> > > > Signed-off-by: Clément Péron <peron.clem@xxxxxxxxx> > > > --- > > > sound/soc/sunxi/sun4i-i2s.c | 22 ++++++++++++++++++++++ > > > 1 file changed, 22 insertions(+) > > > > > > diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c > > > index a23c9f2a3f8c..618bbc5156f1 100644 > > > --- a/sound/soc/sunxi/sun4i-i2s.c > > > +++ b/sound/soc/sunxi/sun4i-i2s.c > > > @@ -48,6 +48,9 @@ > > > #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0) > > > > > > #define SUN4I_I2S_FMT1_REG 0x08 > > > +#define SUN4I_I2S_FMT1_REG_SEXT_MASK BIT(8) > > > +#define SUN4I_I2S_FMT1_REG_SEXT(sext) ((sext) << 8) > > > + > > > #define SUN4I_I2S_FIFO_TX_REG 0x0c > > > #define SUN4I_I2S_FIFO_RX_REG 0x10 > > > > > > @@ -105,6 +108,9 @@ > > > #define SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 7) > > > #define SUN8I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 7) > > > > > > +#define SUN8I_I2S_FMT1_REG_SEXT_MASK GENMASK(5,4) > > > +#define SUN8I_I2S_FMT1_REG_SEXT(sext) ((sext) << 4) > > > + > > > #define SUN8I_I2S_INT_STA_REG 0x0c > > > #define SUN8I_I2S_FIFO_TX_REG 0x20 > > > > > > @@ -663,6 +669,12 @@ static int sun4i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, > > > } > > > regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, > > > SUN4I_I2S_CTRL_MODE_MASK, val); > > > + > > > + /* Set sign extension to pad out LSB with 0 */ > > > + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, > > > + SUN4I_I2S_FMT1_REG_SEXT_MASK, > > > + SUN4I_I2S_FMT1_REG_SEXT(0)); > > > + > > > return 0; > > > } > > > > > > @@ -765,6 +777,11 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, > > > SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, > > > val); > > > > > > + /* Set sign extension to pad out LSB with 0 */ > > > + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, > > > + SUN8I_I2S_FMT1_REG_SEXT_MASK, > > > + SUN8I_I2S_FMT1_REG_SEXT(0)); > > > + > > > return 0; > > > } > > > > > > @@ -867,6 +884,11 @@ static int sun50i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s, > > > SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT, > > > val); > > > > > > + /* Set sign extension to pad out LSB with 0 */ > > > + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, > > > + SUN8I_I2S_FMT1_REG_SEXT_MASK, > > > + SUN8I_I2S_FMT1_REG_SEXT(0)); > > > + > > > > If this is an issue only on the A10 / A20, why are you setting it up on the > > other generations too? > > To keep coherency between all set_soc_format(), and also avoid this > kind of issue for future generation. > As this doesn't cost much after all, and it avoid to rely on default, > but what do you think ? It makes sense, but it should be in the commit log ;) Maxime
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