On Mon, 30 Mar 2020 21:45:20 +0200, Cezary Rojewski wrote: > Update D0 <-> D3 sequence to correctly transition hardware and DSP core > from and to D3. On top of that, set SHIM registers to their recommended > defaults during D0 and D3 proceduces as HW does not reset registers for > us. > > Connected to: > [BUG] bdw-rt5650 DSP boot timeout > https://mailman.alsa-project.org/pipermail/alsa-devel/2019-July/153098.html > > [...] Applied, thanks! [1/1] ASoC: Intel: haswell: Power transition refactor commit: 8ec7d6043263ecf250b9b7c0dd8ade899487538a All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
