Hi Heiner, I love your patch! Yet something to improve: [auto build test ERROR on pci/next] [also build test ERROR on sound/for-next net-next/master net/master linus/master v5.6-rc3 next-20200224] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Heiner-Kallweit/PCI-add-and-use-constant-PCI_STATUS_ERROR_BITS-and-helper-pci_status_get_and_clear_errors/20200225-154725 base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next config: arm-mvebu_v7_defconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 7.5.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree GCC_VERSION=7.5.0 make.cross ARCH=arm If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp@xxxxxxxxx> All errors (new ones prefixed by >>): >> drivers//pci/pci-bridge-emul.c:53:37: error: expected '}' before ';' token .w1c = PCI_STATUS_ERROR_BITS << 16; ^ drivers//pci/pci-bridge-emul.c:98:37: error: expected '}' before ';' token .w1c = PCI_STATUS_ERROR_BITS << 16; ^ vim +53 drivers//pci/pci-bridge-emul.c 40 41 static const struct pci_bridge_reg_behavior pci_regs_behavior[] = { 42 [PCI_VENDOR_ID / 4] = { .ro = ~0 }, 43 [PCI_COMMAND / 4] = { 44 .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 45 PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | 46 PCI_COMMAND_SERR), 47 .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE | 48 PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT | 49 PCI_COMMAND_FAST_BACK) | 50 (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ | 51 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16), 52 .rsvd = GENMASK(15, 10) | ((BIT(6) | GENMASK(3, 0)) << 16), > 53 .w1c = PCI_STATUS_ERROR_BITS << 16; 54 }, 55 [PCI_CLASS_REVISION / 4] = { .ro = ~0 }, 56 57 /* 58 * Cache Line Size register: implement as read-only, we do not 59 * pretend implementing "Memory Write and Invalidate" 60 * transactions" 61 * 62 * Latency Timer Register: implemented as read-only, as "A 63 * bridge that is not capable of a burst transfer of more than 64 * two data phases on its primary interface is permitted to 65 * hardwire the Latency Timer to a value of 16 or less" 66 * 67 * Header Type: always read-only 68 * 69 * BIST register: implemented as read-only, as "A bridge that 70 * does not support BIST must implement this register as a 71 * read-only register that returns 0 when read" 72 */ 73 [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 }, 74 75 /* 76 * Base Address registers not used must be implemented as 77 * read-only registers that return 0 when read. 78 */ 79 [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 }, 80 [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 }, 81 82 [PCI_PRIMARY_BUS / 4] = { 83 /* Primary, secondary and subordinate bus are RW */ 84 .rw = GENMASK(24, 0), 85 /* Secondary latency is read-only */ 86 .ro = GENMASK(31, 24), 87 }, 88 89 [PCI_IO_BASE / 4] = { 90 /* The high four bits of I/O base/limit are RW */ 91 .rw = (GENMASK(15, 12) | GENMASK(7, 4)), 92 93 /* The low four bits of I/O base/limit are RO */ 94 .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK | 95 PCI_STATUS_DEVSEL_MASK) << 16) | 96 GENMASK(11, 8) | GENMASK(3, 0)), 97 98 .w1c = PCI_STATUS_ERROR_BITS << 16; 99 100 .rsvd = ((BIT(6) | GENMASK(4, 0)) << 16), 101 }, 102 103 [PCI_MEMORY_BASE / 4] = { 104 /* The high 12-bits of mem base/limit are RW */ 105 .rw = GENMASK(31, 20) | GENMASK(15, 4), 106 107 /* The low four bits of mem base/limit are RO */ 108 .ro = GENMASK(19, 16) | GENMASK(3, 0), 109 }, 110 111 [PCI_PREF_MEMORY_BASE / 4] = { 112 /* The high 12-bits of pref mem base/limit are RW */ 113 .rw = GENMASK(31, 20) | GENMASK(15, 4), 114 115 /* The low four bits of pref mem base/limit are RO */ 116 .ro = GENMASK(19, 16) | GENMASK(3, 0), 117 }, 118 119 [PCI_PREF_BASE_UPPER32 / 4] = { 120 .rw = ~0, 121 }, 122 123 [PCI_PREF_LIMIT_UPPER32 / 4] = { 124 .rw = ~0, 125 }, 126 127 [PCI_IO_BASE_UPPER16 / 4] = { 128 .rw = ~0, 129 }, 130 131 [PCI_CAPABILITY_LIST / 4] = { 132 .ro = GENMASK(7, 0), 133 .rsvd = GENMASK(31, 8), 134 }, 135 136 [PCI_ROM_ADDRESS1 / 4] = { 137 .rw = GENMASK(31, 11) | BIT(0), 138 .rsvd = GENMASK(10, 1), 139 }, 140 141 /* 142 * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8) 143 * are RO, and bridge control (31:16) are a mix of RW, RO, 144 * reserved and W1C bits 145 */ 146 [PCI_INTERRUPT_LINE / 4] = { 147 /* Interrupt line is RW */ 148 .rw = (GENMASK(7, 0) | 149 ((PCI_BRIDGE_CTL_PARITY | 150 PCI_BRIDGE_CTL_SERR | 151 PCI_BRIDGE_CTL_ISA | 152 PCI_BRIDGE_CTL_VGA | 153 PCI_BRIDGE_CTL_MASTER_ABORT | 154 PCI_BRIDGE_CTL_BUS_RESET | 155 BIT(8) | BIT(9) | BIT(11)) << 16)), 156 157 /* Interrupt pin is RO */ 158 .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)), 159 160 .w1c = BIT(10) << 16, 161 162 .rsvd = (GENMASK(15, 12) | BIT(4)) << 16, 163 }, 164 }; 165 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
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