On Mon, Feb 17, 2020 at 10:59:55AM +0000, Derek [方德義] wrote:
> > Subject: Re: [PATCH 1/2] ASoC: rt5682: Add CCF usage for providing I2S clks
> > > + if (parent_rate != CLK_PLL2_FIN)
> > > + dev_warn(component->dev, "clk %s only support %d Hz input\n",
> > > + clk_name, CLK_PLL2_FIN);
> > > + if (rate != CLK_48) {
> > > + dev_warn(component->dev, "clk %s only support %d Hz output\n",
> > > + clk_name, CLK_48);
> > > + rate = CLK_48;
> > > + }
> > Are these genuine restrictions of the hardware or is this just being
> > hard coded in the driver?
> It's hard coded for an application case.
> Generate a 48kHz clk with a parent 48 MHz clk.
I see... obviously this is really not good quality of implementation
although it doesn't actually break any external interfaces so I guess we
could take it. I would at least want to see some clear comments in both
the code and the changelog explaining that this limitation is just a
temporary hack until a better implementation is done though.
Attachment:
signature.asc
Description: PGP signature
_______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx https://mailman.alsa-project.org/mailman/listinfo/alsa-devel
