Hi Pierre,
[reducing the recipient list ALSA people]
On 12/18/19 4:32 PM, Pierre-Louis Bossart wrote:
> On 12/18/19 3:49 AM, Daniel Mack wrote:
>> Hi,
>>
>> On 12/17/19 8:28 PM, Pierre-Louis Bossart wrote:
>>> On 12/9/19 12:35 PM, Daniel Mack wrote:
>>
>>>> + if (!ad242x_node_is_master(priv->node) &&
>>>> + ((format & SND_SOC_DAIFMT_MASTER_MASK) !=
>>>> SND_SOC_DAIFMT_CBM_CFM)) {
>>>> + dev_err(component->dev, "slave node must be clock master\n");
>>>> + return -EINVAL;
>>>> + }
>>>
>>> It was my understanding that the master node provides the clock to the
>>> bus, so not sure how it could be a clock slave, and conversely how a
>>> slave node could provide a clock to the bus?
>>
>> The slave nodes receive the A2B clock from the master node and then
>> produce digital audio output that is sent to other components such as
>> codecs. Hence, in ASoC terms, they are the clock master.
>>
>> Likewise, as the master node is receiving its clock from other
>> components, it has to be a clock slave in the audio network.
>>
>> Does that make sense?
>
> Your slave node acts as a bridge then, but it seems you don't model the
> bus-facing interface, which has to follow the master clock. Or do you?
Yes, the driver currently only models the SOC-facing side, and that
follows the 'reverse' clocking scheme:
* The master node always receives the clock on the SOC-facing side, and
produces the clock on the bus-facing side.
* The slave node always receives the clock on the bus-facing side, and
produces the clock on the SOC-facing side.
I currently don't see a reason for modelling the bus-facing side in the
ASoC topology at all, but of course that could be added.
But for the SOC-facing side on *slave* nodes, the currently implemented
logic should be correct, no? Do you think it makes sense to add the
bus-side as well?
> Likewise the master has an 'SOC-facing' interface and a bus-facing
> interface. it *could* be master on both if ASRC was supported. The point
> is that the bus-facing interface is not clock slave.
That's right, I need to look into the modes for the master node again.
Maybe the check needs to be relaxed on that end.
Thanks,
Daniel
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