11.12.2019 18:10, Peter De Schrijver пишет: > On Tue, Dec 10, 2019 at 08:41:56PM +0300, Dmitry Osipenko wrote: > > .. > >>> >>> PMC clock gate is based on the state of CLKx_ACCEPT_REQ and FORCE_EN >>> like explained above. >>> >>> CLKx_ACCEPT_REQ is 0 default and FORCE_EN acts as gate to enable/disable >>> EXTPERIPH clock output to PMC CLK_OUT_1/2/3. >> >> [and to enable OSC as well] >> >>> So I believe we need to register as MUX and Gate rather than as a single >>> clock. Please confirm. >> >> 1. The force-enabling is applied to both OSC and EXTERN sources of >> PMC_CLK_OUT_x by PMC at once. >> >> 2. Both of PMC's force-enabling and OSC/EXTERN selection is internal to PMC. >> >> Should be better to define it as a single "pmc_clk_out_x". I don't see >> any good reasons for differentiating PMC's Gate from the MUX, it's a >> single hardware unit from a point of view of the rest of the system. >> >> Peter, do you have any objections? > > The reason to have separate gate and mux clocks, is to preserve compatibility > with existing users. > Otherwise the current users would need to figure out if there's a > single clock or 2 clocks to configure. I don't think adding that code in > each user is worth it only to have a sligthly nicer modelling of the > hardware. Could you please clarify what do you mean by the "existing users"? AFAIK, nothing in kernel uses mux clocks. _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx https://mailman.alsa-project.org/mailman/listinfo/alsa-devel
