On Wed, 2019-10-16 at 13:59 +0800, Jiaxin Yu wrote:
> From: "yong.liang" <yong.liang@xxxxxxxxxxxx>
>
> Add reset controller API in watchdog driver.
> Besides watchdog, MTK toprgu module also provide sub-system (eg, audio,
> camera, codec and connectivity) software reset functionality.
>
> Signed-off-by: yong.liang <yong.liang@xxxxxxxxxxxx>
Jiaxin,
Since you send this patch, you should add your signed-off-by tag here as
well.
This looks good to me otherwise. Feel free to add my reviewed by if you
want:
Reviewed-by: Yingjoe Chen <yingjoe.chen@xxxxxxxxxxxx>
Joe.C
> ---
> drivers/watchdog/Kconfig | 1 +
> drivers/watchdog/mtk_wdt.c | 111 ++++++++++++++++++++++++++++++++++++-
> 2 files changed, 111 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index 2e07caab9db2..629249fe5305 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -717,6 +717,7 @@ config MEDIATEK_WATCHDOG
> tristate "Mediatek SoCs watchdog support"
> depends on ARCH_MEDIATEK || COMPILE_TEST
> select WATCHDOG_CORE
> + select RESET_CONTROLLER
> help
> Say Y here to include support for the watchdog timer
> in Mediatek SoCs.
> diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
> index 9c3d0033260d..d29484c7940a 100644
> --- a/drivers/watchdog/mtk_wdt.c
> +++ b/drivers/watchdog/mtk_wdt.c
> @@ -9,6 +9,9 @@
> * Based on sunxi_wdt.c
> */
>
> +#include <dt-bindings/reset-controller/mt2712-resets.h>
> +#include <dt-bindings/reset-controller/mt8183-resets.h>
> +#include <linux/delay.h>
> #include <linux/err.h>
> #include <linux/init.h>
> #include <linux/io.h>
> @@ -16,10 +19,12 @@
> #include <linux/module.h>
> #include <linux/moduleparam.h>
> #include <linux/of.h>
> +#include <linux/of_device.h>
> #include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/slab.h>
> #include <linux/types.h>
> #include <linux/watchdog.h>
> -#include <linux/delay.h>
>
> #define WDT_MAX_TIMEOUT 31
> #define WDT_MIN_TIMEOUT 1
> @@ -44,6 +49,9 @@
> #define WDT_SWRST 0x14
> #define WDT_SWRST_KEY 0x1209
>
> +#define WDT_SWSYSRST 0x18U
> +#define WDT_SWSYS_RST_KEY 0x88000000
> +
> #define DRV_NAME "mtk-wdt"
> #define DRV_VERSION "1.0"
>
> @@ -53,8 +61,99 @@ static unsigned int timeout;
> struct mtk_wdt_dev {
> struct watchdog_device wdt_dev;
> void __iomem *wdt_base;
> + spinlock_t lock; /* protects WDT_SWSYSRST reg */
> + struct reset_controller_dev rcdev;
> +};
> +
> +struct mtk_wdt_data {
> + int sw_rst_num;
> };
>
> +static const struct mtk_wdt_data mt2712_data = {
> + .sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
> +};
> +
> +static const struct mtk_wdt_data mt8183_data = {
> + .sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
> +};
> +
> +static int toprgu_reset_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + unsigned int tmp;
> + unsigned long flags;
> + struct mtk_wdt_dev *data =
> + container_of(rcdev, struct mtk_wdt_dev, rcdev);
> +
> + spin_lock_irqsave(&data->lock, flags);
> +
> + tmp = __raw_readl(data->wdt_base + WDT_SWSYSRST);
> + tmp |= BIT(id);
> + tmp |= WDT_SWSYS_RST_KEY;
> + writel(tmp, data->wdt_base + WDT_SWSYSRST);
> +
> + spin_unlock_irqrestore(&data->lock, flags);
> +
> + return 0;
> +}
> +
> +static int toprgu_reset_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + unsigned int tmp;
> + unsigned long flags;
> + struct mtk_wdt_dev *data =
> + container_of(rcdev, struct mtk_wdt_dev, rcdev);
> +
> + spin_lock_irqsave(&data->lock, flags);
> +
> + tmp = __raw_readl(data->wdt_base + WDT_SWSYSRST);
> + tmp &= ~BIT(id);
> + tmp |= WDT_SWSYS_RST_KEY;
> + writel(tmp, data->wdt_base + WDT_SWSYSRST);
> +
> + spin_unlock_irqrestore(&data->lock, flags);
> +
> + return 0;
> +}
> +
> +static int toprgu_reset(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + int ret;
> +
> + ret = toprgu_reset_assert(rcdev, id);
> + if (ret)
> + return ret;
> +
> + return toprgu_reset_deassert(rcdev, id);
> +}
> +
> +static const struct reset_control_ops toprgu_reset_ops = {
> + .assert = toprgu_reset_assert,
> + .deassert = toprgu_reset_deassert,
> + .reset = toprgu_reset,
> +};
> +
> +static int toprgu_register_reset_controller(struct platform_device *pdev,
> + int rst_num)
> +{
> + int ret;
> + struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
> +
> + spin_lock_init(&mtk_wdt->lock);
> +
> + mtk_wdt->rcdev.owner = THIS_MODULE;
> + mtk_wdt->rcdev.nr_resets = rst_num;
> + mtk_wdt->rcdev.ops = &toprgu_reset_ops;
> + mtk_wdt->rcdev.of_node = pdev->dev.of_node;
> + ret = reset_controller_register(&mtk_wdt->rcdev);
> + if (ret != 0)
> + dev_err(&pdev->dev,
> + "couldn't register wdt reset controller: %d\n", ret);
> + return ret;
> +}
> +
> static int mtk_wdt_restart(struct watchdog_device *wdt_dev,
> unsigned long action, void *data)
> {
> @@ -155,6 +254,7 @@ static int mtk_wdt_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> struct mtk_wdt_dev *mtk_wdt;
> + struct mtk_wdt_data *wdt_data;
> int err;
>
> mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL);
> @@ -190,6 +290,13 @@ static int mtk_wdt_probe(struct platform_device *pdev)
> dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
> mtk_wdt->wdt_dev.timeout, nowayout);
>
> + wdt_data = (struct mtk_wdt_data *)of_device_get_match_data(dev);
> + if (wdt_data) {
> + err = toprgu_register_reset_controller(pdev,
> + wdt_data->sw_rst_num);
> + if (err)
> + return err;
> + }
> return 0;
> }
>
> @@ -218,7 +325,9 @@ static int mtk_wdt_resume(struct device *dev)
> #endif
>
> static const struct of_device_id mtk_wdt_dt_ids[] = {
> + { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
> { .compatible = "mediatek,mt6589-wdt" },
> + { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
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