On Wed, 2007-06-06 at 18:36 +0530, Nobin Mathew wrote:
> Liam,
>
> I have one suggestion.
>
> Can we use this
>
> if (rtd->codec_dai->ops.trigger) {
> ret = rtd->codec_dai->ops.trigger(substream, cmd);
> if (ret < 0)
> return ret;
> }
>
> if (rtd->cpu_dai->ops.trigger) {
> ret = rtd->cpu_dai->ops.trigger(substream, cmd);
> if (ret < 0)
> return ret;
> }
> if (platform->pcm_ops->trigger) {
> ret = platform->pcm_ops->trigger(substream, cmd);
> if (ret < 0)
> return ret;
> }
>
> Instead of
>
> if (rtd->codec_dai->ops.trigger) {
> ret = rtd->codec_dai->ops.trigger(substream, cmd);
> if (ret < 0)
> return ret;
> }
>
> if (platform->pcm_ops->trigger) {
> ret = platform->pcm_ops->trigger(substream, cmd);
> if (ret < 0)
> return ret;
> }
>
> if (rtd->cpu_dai->ops.trigger) {
> ret = rtd->cpu_dai->ops.trigger(substream, cmd);
> if (ret < 0)
> return ret;
> }
>
>
> That means trigger the Cpu before pcm. Because most of the controllers
> needs to be initialized and triggered before external DMA is
> triggered.
>
> Correct me if i am going wrong.
The current ordering allows the DMA to trigger before the I2S/PCM
controller triggers. This means that the DMA should be ready before the
controller generates any FIFO DMA interrupt requests. Fwiw, this seems
to work well on most machines atm.
> This was causing so many problems in my hardware.
What sort of problems. Underruns ? What does your trigger do in each
case ?
Is it possible to set some of your controller up in prepare() and then
hit it's enable bit in trigger ?
Liam
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