> Looks fine, too.
> Could you post a patch with a short patch summary and sign-off to
> apply to the upstream tree?
ice1724.c:
-------------
* always set 256fs in SPDIF master clock mode
prodigy192.c:
-----------------
* disable deemphasis filter in AK4114
Signed-off-by: Pavel Hofman <dustin@xxxxxxxxx>
diff -r 05d4738cc065 pci/ice1712/ice1724.c
--- a/pci/ice1712/ice1724.c Mon Apr 23 17:17:48 2007 +0200
+++ b/pci/ice1712/ice1724.c Mon Apr 23 23:45:00 2007 +0200
@@ -1666,7 +1666,11 @@ static int snd_vt1724_pro_internal_clock
spin_lock_irq(&ice->reg_lock);
oval = inb(ICEMT1724(ice, RATE));
if (ucontrol->value.enumerated.item[0] == spdif) {
+ unsigned char i2s_oval;
outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
+ /* setting 256fs */
+ i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));
+ outb( i2s_oval & ~VT1724_MT_I2S_MCLK_128X, ICEMT1724(ice, I2S_FORMAT));
} else {
rate = rates[ucontrol->value.integer.value[0] % 15];
if (rate <= get_max_rate(ice)) {
diff -r 05d4738cc065 pci/ice1712/prodigy192.c
--- a/pci/ice1712/prodigy192.c Mon Apr 23 17:17:48 2007 +0200
+++ b/pci/ice1712/prodigy192.c Tue Apr 24 00:20:38 2007 +0200
@@ -26,6 +26,11 @@
* CCLK (pin 34) -- GPIO9 pin 76
* CSN (pin 35) -- GPIO8 pin 75
* - output data Mode 7 (24bit, I2S, slave)
+ * - both MCKO1 and MCKO2 of ak4114 are fed to FPGA, which
+ * outputs master clock to SPMCLKIN of ice1724. Experimentally I found out
+ * that only a combination of OCKS0=1, OCKS1=1 (128fs, 64fs output) and
+ * ice1724 - VT1724_MT_I2S_MCLK_128X=0 (256fs input) yields correct
+ * sampling rate. That means the the FPGA doubles the MCK01 rate.
*
* Copyright (c) 2003 Takashi Iwai <tiwai@xxxxxxx>
* Copyright (c) 2003 Dimitromanolakis Apostolos <apostol@xxxxxxxxxxxxxx>
@@ -714,7 +719,8 @@ static int prodigy192_ak4114_init(struct
{
static const unsigned char ak4114_init_vals[] = {
AK4114_RST | AK4114_PWN | AK4114_OCKS0 | AK4114_OCKS1,
- AK4114_DIF_I24I2S, /* ice1724 expects I2S and provides clock */
+ AK4114_DIF_I24I2S | AK4114_DEM0 , /* ice1724 expects I2S and provides clock,
+ DEM0 disables the deemphasis filter */
AK4114_TX1E,
AK4114_EFH_1024 | AK4114_DIT, /* default input RX0 */
0,
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