Re: [PATCH] x86_64: Fix for AMD SME issue

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On 2022/08/01 15:22, lijiang wrote:

>>> @@ -1938,6 +1946,7 @@ x86_64_pud_offset(ulong pgd_pte, ulong vaddr, int
>> verbose, int IS_XEN)
>>>        FILL_PUD(pud_paddr, PHYSADDR, PAGESIZE());
>>>        pud = ((ulong *)pud_paddr) + pud_index(vaddr);
>>>        pud_pte = ULONG(machdep->pud + PAGEOFFSET(pud));
>>> +     pud_pte &= ~machdep->machspec->sme_mask;
>>
>> Taking this for example, the pud_pte is masked here..
>>
>>
> Good questions. This was based on two considerations:
> [1] ensure to display the printing information as below:
>           ...
>           P4D: 761c01a70 => 761c02067
>           PUD: 761c02b28 => 16bea5063
>                                              ^^^^^^^^^^
>        Otherwise, it will display the address of PUD with the C-bit.
>        Or Remove the C-bit when printing information?
> +    fprintf(fp, "   PUD: %lx => %lx\n", (ulong)pud, pud_pte &
> ~machdep->machspec->sme_mask);

I thought it might be good to display the raw pte value, but ok,
the current way also looks good.

> 
> [2] consider the cases of using hugepage.
>       -On this machine, it supports 1G and 2M hugepage according to the
> vmcore.
> 
> 
>>   >       if (verbose) {
>>>                if (IS_XEN)
>>>                        fprintf(fp, "   PUD: %lx => %lx [machine]\n",
>> (ulong)pud, pud_pte);
>>> @@ -1960,6 +1969,7 @@ x86_64_pmd_offset(ulong pud_pte, ulong vaddr, int
>> verbose, int IS_XEN)
>>>        ulong pmd_pte;
>>>
>>>        pmd_paddr = pud_pte & PHYSICAL_PAGE_MASK;
>>> +     pmd_paddr &= ~machdep->machspec->sme_mask;
>>
>> and also here the pud_pte is masked again.  Is this needed?
>>
>>
> They are needed, otherwise some crash commands may not work well, for
> example:
> ...
> kmem: seek error: kernel virtual address: ffedfea0c627ec28  type: "page
> inuse"

ah ok, x86_64_kpgd_offset returns the pointer of a pgd entry, so
x86_64_p4d_offset and x86_64_pud_offset need to mask the pgd entry
before using it.  Let's go with this.

Acked-by: Kazuhito Hagio <k-hagio-ab@xxxxxxx>

Thanks,
Kazu
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