On Fri, Jan 22, 2021 at 08:48:55AM +0100, Petr Tesarik wrote: > IIUC the only reason for having a physical mask at all is that all page > table bits beyond the current architectural limit are marked as > reserved by Intel, so they could theoretically be used for any purpose > in a future revision of the architecture. Intel has always recommended > to initialize reserved bits to zero, but I think that crash utility > developers are quite conservative and afraid of introducing regressions > for cases that are known to work, so whenever they introduce a new > feature (such as 5-level paging), they try to preserve the existing > working cases with absolutely no change. Well the bits above bit 51 need to be masked out. The AMD64 Architecture Programmer’s Manual (Volume 2: System Programming) shows these as "Available", meaning "not interpreted by the processor" and the OS can use them for whatever purpose. And bit 63 is NX. So we do need to have a physical mask only covering bits 12-51 which is the physical address of the next level page table. The question is why have masks shorter than 52 bits for systems with physical addresses shorter than 52 bits. These, AFAICT need to be 0 in the PTE and thus don't need to be masked out to obtain the address. -- Jiri Bohac <jbohac@xxxxxxx> SUSE Labs, Prague, Czechia -- Crash-utility mailing list Crash-utility@xxxxxxxxxx https://www.redhat.com/mailman/listinfo/crash-utility
