[PATCH 4/5] soundwire: amd: add soundwire host wake interrupt enable/disable sequence

[Vijendar Mukunda <Vijendar.Mukunda@xxxxxxx>]

SoundWire host wake interrupt will be asserted based on below
pre-conditions for ACP7.0 & ACP7.1 platforms for SoundWire poweroff mode.
- ACP device should be in D0 state.
- SoundWire manager instance should be in D3 state.
- SoundWire manager device state should be set to D3.

Implement code changes to enable/disable SoundWire host wake mask and
SoundWire device state for ACP7.0 & ACP7.1 platforms for SoundWire
poweroff mode as mentioned below.
- Enable SoundWire host wake mask during runtime suspend sequence.
- Disable SoundWire host wake mask during resume sequence.
- Set the SoundWire device state to D3 during runtime suspend sequence and
set the device state to D0 state during resume sequence by programming
'AMD_SDW_DEVICE_STATE' register.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@xxxxxxx>
---
 drivers/soundwire/amd_manager.c | 45 +++++++++++++++++++++++++++++++++
 drivers/soundwire/amd_manager.h |  7 +++++
 2 files changed, 52 insertions(+)

diff --git a/drivers/soundwire/amd_manager.c b/drivers/soundwire/amd_manager.c
index 9eb8d345b527..6f9d9f765a20 100644
--- a/drivers/soundwire/amd_manager.c
+++ b/drivers/soundwire/amd_manager.c
@@ -143,6 +143,47 @@ static void amd_sdw_wake_enable(struct amd_sdw_manager *amd_manager, bool enable
 	writel(wake_ctrl, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
 }
 
+static int amd_sdw_host_wake_enable(struct amd_sdw_manager *amd_manager, bool enable)
+{
+	u32 intr_cntl1;
+	u32 sdw_host_wake_irq_mask;
+	u32 sdw_dev_state_mask;
+	u32 target_dev_state;
+	u32 sdw_dev_state;
+
+	if (!amd_manager->wake_en_mask)
+		return 0;
+
+	switch (amd_manager->instance) {
+	case ACP_SDW0:
+		sdw_host_wake_irq_mask = AMD_SDW0_HOST_WAKE_INTR_MASK;
+		sdw_dev_state_mask = AMD_SDW0_DEVICE_STATE_MASK;
+		break;
+	case ACP_SDW1:
+		sdw_host_wake_irq_mask = AMD_SDW1_HOST_WAKE_INTR_MASK;
+		sdw_dev_state_mask = AMD_SDW1_DEVICE_STATE_MASK;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	intr_cntl1 = readl(amd_manager->acp_mmio + ACP_EXTERNAL_INTR_CNTL(ACP_SDW1));
+	if (enable) {
+		intr_cntl1 |= sdw_host_wake_irq_mask;
+		target_dev_state = AMD_SDW_DEVICE_STATE_D3;
+	} else {
+		intr_cntl1 &= ~sdw_host_wake_irq_mask;
+		target_dev_state = AMD_SDW_DEVICE_STATE_D0;
+	}
+	writel(intr_cntl1, amd_manager->acp_mmio + ACP_EXTERNAL_INTR_CNTL(ACP_SDW1));
+	sdw_dev_state = readl(amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE);
+	amd_updatel(amd_manager->acp_mmio, AMD_SDW_DEVICE_STATE, sdw_dev_state_mask,
+		    target_dev_state);
+	sdw_dev_state = readl(amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE);
+	dev_dbg(amd_manager->dev, "AMD_SDW_DEVICE_STATE:0x%x\n", sdw_dev_state);
+	return 0;
+}
+
 static void amd_sdw_ctl_word_prep(u32 *lower_word, u32 *upper_word, struct sdw_msg *msg,
 				  int cmd_offset)
 {
@@ -1191,6 +1232,8 @@ static int __maybe_unused amd_suspend_runtime(struct device *dev)
 		return amd_sdw_clock_stop(amd_manager);
 	} else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {
 		amd_sdw_wake_enable(amd_manager, true);
+		if (amd_manager->acp_rev >= ACP70_PCI_REV_ID)
+			amd_sdw_host_wake_enable(amd_manager, true);
 		ret = amd_sdw_clock_stop(amd_manager);
 		if (ret)
 			return ret;
@@ -1217,6 +1260,8 @@ static int __maybe_unused amd_resume_runtime(struct device *dev)
 		return amd_sdw_clock_stop_exit(amd_manager);
 	} else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {
 		writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance));
+		if (amd_manager->acp_rev >= ACP70_PCI_REV_ID)
+			amd_sdw_host_wake_enable(amd_manager, false);
 		val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
 		if (val) {
 			val |= AMD_SDW_CLK_RESUME_REQ;
diff --git a/drivers/soundwire/amd_manager.h b/drivers/soundwire/amd_manager.h
index 30244a31c21c..18faef593865 100644
--- a/drivers/soundwire/amd_manager.h
+++ b/drivers/soundwire/amd_manager.h
@@ -194,6 +194,13 @@
 #define AMD_SDW_CLK_RESUME_DONE				3
 #define AMD_SDW_WAKE_STAT_MASK				BIT(16)
 #define AMD_SDW_WAKE_INTR_MASK				BIT(16)
+#define AMD_SDW0_HOST_WAKE_INTR_MASK			BIT(22)
+#define AMD_SDW1_HOST_WAKE_INTR_MASK			BIT(23)
+#define AMD_SDW_DEVICE_STATE				0x1430
+#define AMD_SDW0_DEVICE_STATE_MASK			3
+#define AMD_SDW1_DEVICE_STATE_MASK			0xc
+#define AMD_SDW_DEVICE_STATE_D0				0
+#define AMD_SDW_DEVICE_STATE_D3				3
 
 static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] = {
 	AMD_SDW_DEFAULT_CLK_FREQ,
-- 
2.34.1