Re: [bug report] ASoC: amd: acp: refactor acp i2s clock generation code

[syed saba kareem <ssabakar@xxxxxxx>]

On 10/30/23 14:34, Dan Carpenter wrote:
> Hello Syed Saba Kareem,
>
> The patch 40f74d5f09d7: "ASoC: amd: acp: refactor acp i2s clock
> generation code" from Oct 21, 2023 (linux-next), leads to the
> following Smatch static checker warning:
>
> 	sound/soc/amd/acp/acp-i2s.c:59 acp_set_i2s_clk()
> 	warn: odd binop '0x0 & 0x2'
>
> sound/soc/amd/acp/acp-i2s.c
>      35 static inline void acp_set_i2s_clk(struct acp_dev_data *adata, int dai_id)
>      36 {
>      37         u32 i2s_clk_reg, val;
>      38         struct acp_chip_info *chip;
>      39         struct device *dev;
>      40
>      41         dev = adata->dev;
>      42         chip = dev_get_platdata(dev);
>      43         switch (dai_id) {
>      44         case I2S_SP_INSTANCE:
>      45                 i2s_clk_reg = ACP_I2STDM0_MSTRCLKGEN;
>      46                 break;
>      47         case I2S_BT_INSTANCE:
>      48                 i2s_clk_reg = ACP_I2STDM1_MSTRCLKGEN;
>      49                 break;
>      50         case I2S_HS_INSTANCE:
>      51                 i2s_clk_reg = ACP_I2STDM2_MSTRCLKGEN;
>      52                 break;
>      53         default:
>      54                 i2s_clk_reg = ACP_I2STDM0_MSTRCLKGEN;
>      55                 break;
>      56         }
>      57
>      58         val  = I2S_MASTER_MODE_ENABLE;
> --> 59         val |= I2S_MODE_ENABLE & BIT(1);
>                        ^^^^^^^^^^^^^^^
> This is zero.
>
> #define I2S_MODE_ENABLE                 0
>
> So this line is a no-op.  What's happening here?

This has been already identified in the below thread.

https://lore.kernel.org/alsa-devel/af1a7eff-bc5e-43a9-99c0-9f26a546f537@xxxxxxx/

Will provide a fix.

>      60
>      61         switch (chip->acp_rev) {
>      62         case ACP63_DEV:
>      63                 val |= FIELD_PREP(ACP63_LRCLK_DIV_FIELD, adata->lrclk_div);
>      64                 val |= FIELD_PREP(ACP63_BCLK_DIV_FIELD, adata->bclk_div);
>      65                 break;
>      66         default:
>      67                 val |= FIELD_PREP(LRCLK_DIV_FIELD, adata->lrclk_div);
>      68                 val |= FIELD_PREP(BCLK_DIV_FIELD, adata->bclk_div);
>      69         }
>      70         writel(val, adata->acp_base + i2s_clk_reg);
>      71 }
>
> regards,
> dan carpenter