Re: assigning PCI addresses with bus > 0x09

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On 1/3/19 5:22 AM, Riccardo Ravaioli wrote:
On Thu, 20 Dec 2018 at 15:39, Laine Stump <laine@xxxxxxxxxx <mailto:laine@xxxxxxxxxx>> wrote:

    I think you're right. Each bus requires some amount of IO space, and I
    thought I recalled someone saying that all of the available IO space is
    exhausted after 7 or 8 buses. [...]


Laine,

Do you have by any chance a link to a page explaining this in more details?
Thanks again! :)

No, sorry. There are mentions of it in bugzilla records (e.g. https://bugzilla.redhat.com/show_bug.cgi?id=1067777 ) but all the info I have is just recalled from email and irc conversations over the last 3-4 years. Basically the amount of IO address space is limited, and SeaBIOS allocates some minimum-sized chunk of that for each PCI controller that is probed and "seems to need IO address space for its devices". After 8 or so controllers, all the space is used up.

You can avoid the IO address space limit if you're using a PCI Express based machinetype, *and* all PCIe devices, but you'll run up against different limits that need to be worked around in a different way - PCIe devices are required to be usable with no IO address space (and so QEMU specifically creates the PCIe controllers beyond pcie-root without any). But each PCIe controller only has a single slot (with 8 functions), each consumes a "bus number" and the bus number is an 8-bit value, so you're limited to 256 total (x8 if you don't need hotplug and don't mind manually assigning addresses).

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