Though I don't quite understand it well enough, but it looks
wrong to read the control register from the device, and then
write to its parent twice, while doing the secondary bus reset.
---
src/util/pci.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/util/pci.c b/src/util/pci.c
index 0742d07..c3f1b2b 100644
--- a/src/util/pci.c
+++ b/src/util/pci.c
@@ -642,7 +642,7 @@ pciTrySecondaryBusReset(pciDevice *dev,
/* Read the control register, set the reset flag, wait 200ms,
* unset the reset flag and wait 200ms.
*/
- ctl = pciRead16(dev, PCI_BRIDGE_CONTROL);
+ ctl = pciRead16(parent, PCI_BRIDGE_CONTROL);
pciWrite16(parent, PCI_BRIDGE_CONTROL, ctl | PCI_BRIDGE_CTL_RESET);
--
1.7.7.3
--
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