On Wed, May 15, 2024 at 06:06:56PM +0100, Daniel P. Berrangé wrote: > Date: Wed, 15 May 2024 18:06:56 +0100 > From: "Daniel P. Berrangé" <berrange@xxxxxxxxxx> > Subject: Re: [PATCH 1/2] hw/core: allow parameter=1 for SMP topology on any > machine > > On Tue, May 14, 2024 at 11:49:40AM +0800, Zhao Liu wrote: > > > I'm failing to see what real world technical problems QEMU faces > > > with a parameter being set to '1' by a mgmt app, when QEMU itself > > > treats all omitted values as being '1' anyway. > > > > > > If we're trying to faithfully model the real world, then restricting > > > the topology against machine types though still looks inherantly wrong. > > > The valid topology ought to be constrained based on the named CPU model. > > > eg it doesn't make sense to allow 'dies=4' with a Skylake CPU model, > > > only an EPYC CPU model, especially if we want to model cache info in > > > a way that matches the real world silicon better. > > > > Thanks for figuring out this. This issue is related with Intel CPU > > cache model: currently Intel code defaults L3 shared at die level. > > This could be resolved by defining the accurate default cache topology > > level for CPU model and make Intel CPU models share L3 at package level > > except only Cascadelake. > > > > Then user could define any other topology levels (die/module) for > > Icelake and this won't change the cache topology, unless the user adds > > more sockets or further customizes the cache topology in another way [1]. > > Do you agree with this solution? > > Broadly speaking yes. Historically we have created trouble for > ourselves (and or our users) by allowing creation of "wierd" > guest CPU models, which don't resemble those which can be found > in real world silicon. Problems specifically have been around > unsual combinations of CPUID features eg user enabled X, but not Y, > where real silicon always has X + Y enabled, and guest OS assumed > this is always the case. > > So if our named CPU models can more faithfully match what you might > see in terms of cache topology in the real world, that's likely to > be a good thing. Good to know what you think, it's the important guide for our work. > > > As above, I think that restrictions based on machine type, while nice and > > > simple, are incorrect long term. If we did impose restrictions based on > > > CPU model, then we could trivially expose this info to mgmt apps via the > > > existing mechanism for querying supported CPU models. Limiting based on > > > CPU model, however, has potentially greater back compat issues, though > > > it would be strictly more faithful to hardware. > > > > I think as long as the default cache topology model is clearly defined, > > users can further customize the CPU topology and adjust the cache > > topology based on it. After all, topology is architectural, not CPU > > model-specific (linux support for topology does not take into account > > specific CPU models). > > > > For example, x86, for simplicity, can we assume that all x86 CPU models > > support all x86 topology levels (thread/core/module/die/package) without > > making distinctions based on specific CPU models? > > Hmm, true, if we have direct control over cache topology, the > CPU topology is less critical. I'd still be wary of suggesting > it is a good idea to use CPU topology configs that don't reflect > something the CPU vendor has concievably used in real silicon. Thank you! Yes, besides cache, it may affect other features like Anthony's RAPL support, MSR is (die/package) topology-aware. There's still a lot of open here, I'll take your warning into serious consideration. > > That way as long as the user doesn't change the default topology, then > > Guest's cache and other topology information won't be "corrupted". > > > And there's one more question, does this rollback mean that smp's > > parameters must have compatible default values for all architectures? > > Historically we preferred "sockets", when filling missing topology, > then more recently we switched to prefer "cores", since high core > counts are generally more common in real world than high socket > counts. > > In theory at some point, one might want to fill in 'dies > 0' for > EPYC, or 'modules > 0' for appropriate Intel CPU models, but doing > the reverse while theoretically valid, would be wierd as no such > topology would exist in real silicon. > > Ultimately if you're allowing QEMU guest vCPUs threads to float > freely across host CPUs, there is little point in setting dies/ > modules/threads to a value other than 1, because the guest OS > won't benefit from understanding cache differences for dies/ > modules/threads/etc, if the vCPU can be moved between host CPUs > at any time by the host OS scheduler. > > Fine grained control over dies/modules/threads only makes more > sense if you have strictly pinning vCPU threads 1:1 to host CPUs > > IOW, simply preferring "cores" for everything is a reasonable > default long term plan for everything, unless the specific > architecture target has no concept of "cores". Thank you very much for your education, it has helped me understand the meaning of SMP much better! It makes sense to default the cache topology configuration to core, I'll check further to see if it would conflict with the current x86 default cache topology encoding model and how to defuse the potential conflict. The CPU topology building is centralized in the general SMP code, while cache topology is scattered throughout the architectures' code, which is a significant difference between the two. I'll refresh the smp cache series later. Regards, Zhao
