On Tue, Dec 19, 2023 at 11:52:03AM +0800, lixianglai wrote: > > So does loongarch actually have ioapic support? Just making sure. I'm > > surprised because apparently no other non-x86 architecture supports > > it... > > Yes, loongarch does have IOAPIC, but this feature has no effect on loongarch > at this stage, I will cut it first to simplify the committed code. > > In addition, I have a question, if I understand correctly, the IOAPIC here > should be the device interrupt controller, which is located in the bridge > chip, > > it is called IOAPIC under x86, PCH_PIC under loongarch, and GIC under arm. > > The kernel_irqchip attribute of the machine parameter in qemu corresponding > to the function VIR_DOMAIN_FEATURE_IOAPIC determines > > whether the device interrupt controller is simulated in qemu or kvm. So arm > also has such a need, but why doesn't arm add? Okay, so x86's IOAPIC is controlled by the <ioapic> element, while Arm's GIC uses the <gic> element. By that logic, loongarch should probably introduce a <phc-pic> element. It's a bit silly that we need a separate element per architecture, especially considering that most of the time we just want to control the kernel_irqchip flag. Case in point, as you noticed Arm doesn't expose the ability to configure that at the moment. On the other hand, additional arch-features might show up in the future, at which point the separate element would start making sense. See GIC for an example. Overall, if you don't have a pressing need to expose the ability to control the kernel_irqchip flag I would just avoid doing anything about it now and leave the decision for another day and, possibly, person :) -- Andrea Bolognani / Red Hat / Virtualization _______________________________________________ Devel mailing list -- devel@xxxxxxxxxxxxxxxxx To unsubscribe send an email to devel-leave@xxxxxxxxxxxxxxxxx
