On Wed, Feb 22, 2023 at 09:51:57AM +0000, Daniel P. Berrangé wrote: > On Wed, Feb 22, 2023 at 09:11:13AM +0000, Bernhard Beschow wrote: > > Are there any plans or ideas to support 128 bit architectures > > such as CHERI in the future? There is already a QEMU fork > > implementing CHERI for RISC V [1]. Also ARM has developed an > > experimental hardware implementation of CHERI within the Morello > > project where Linaro is involved as well, although the QEMU > > implementation is performed by the University of Cambridge [2]. > > If 128 bit hardware exists and has real world non-toy usage, > then a request to support it in QEMU is essentially inevitable. > > > I'm asking because once we deeply bake in the assumption that > > host size >= guest size then adding such architectures will > > become much harder. > > Yep, that is a risk. I can second that. Better keep it in the code and deal with it. Maybe those specific parts can be implemented in such a way that it can easily become a noop on host size >= guest size. With regards, Reinoud
