On Tue, Oct 04, 2022 at 10:17:18PM +0200, Jiri Denemark wrote:
> > On Tue, Oct 04, 2022 at 07:35:31PM +0200, Jiri Denemark wrote:
> > > On Tue, Oct 04, 2022 at 17:34:34 +0100, Daniel P. Berrangé wrote:
> > > > On Tue, Oct 04, 2022 at 04:28:53PM +0200, Jiri Denemark wrote:
> > > > > We already show whether a specific CPU model is usable on the current
> > > > > host without modification via the 'usable' attribute of each CPU model.
> > > > > But it may be useful to actually see what features are blocking each CPU
> > > > > model from being usable. Especially when we already fetch the info from
> > > > > QEMU and propagating it to domain capabilities XML is all we need to do.
> > > >
> > > > > diff --git a/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml b/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml
> > > > > index dab12e5888..8ca9e8d2b2 100644
> > > > > --- a/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml
> > > > > +++ b/tests/domaincapsdata/qemu_4.2.0-q35.x86_64.xml
> > > > > @@ -63,7 +63,7 @@
> > > > > <mode name='custom' supported='yes'>
> > > > > <model usable='yes' vendor='unknown'>qemu64</model>
> > > > > <model usable='yes' vendor='unknown'>qemu32</model>
> > > > > - <model usable='no' vendor='AMD'>phenom</model>
> > > > > + <model usable='no' vendor='AMD' blockers='mmxext,fxsr_opt,3dnowext,3dnow,sse4a,npt'>phenom</model>
> > > >
> > > > This is an XML design anti-pattern, because it invents a data format
> > > > inside the attribute which the caller then has to further parse.
> > > >
> > > > If we want to expose this, it needs to be with child elements IMHO,
> > > > but yes it will be more much more verbose.
> > >
> > > You're absolutely right, but that's the only option we have I'm afraid.
> > > Mixing subelements and text nodes is a much worse anti-pattern. I wish
> > > the model name was in an attribute, but it isn't and having
> > >
> > > <model usable='no' vendor='AMD'>
> > > <blocker name='mmxext'/>
> > > phenom
> > > </model>
> > >
> > > is just insane :-(
> >
> > True, I wonder if there's a different approach to the overall problem
> > that would be better.
>
> Actually a third option just came to my mind. It's not ideal either, but
> at least it would be a proper XML :-)
>
> <mode name='custom' supported='yes'>
> <model usable='yes' vendor='unknown'>qemu64</model>
> <model usable='no' vendor='AMD'>phenom</model>
> <blockers model='phenom'>
> <feature name='mmxext'/>
> <feature name='fxsr_opt'/>
> ...
> </blockers>
> <model ...>...</model>
> ...
> </mode>
Actually, looking atr this in practice, I don't think we should be
including this information in domcapabilities at all. It gets
waaaaaaaay too verbose, even with the custom syntax in this current
patch impl. Take a look at this from one of my VMs, which uses the
qemu64 model, and thus lacks a huge number of features:
<model fallback='forbid'>Opteron_G3</model>
<model usable='yes' vendor='unknown'>qemu64</model>
<model usable='yes' vendor='unknown'>qemu32</model>
<model usable='no' vendor='AMD' blockers='fxsr-opt'>phenom</model>
<model usable='yes' vendor='unknown'>pentium3</model>
<model usable='yes' vendor='unknown'>pentium2</model>
<model usable='yes' vendor='unknown'>pentium</model>
<model usable='yes' vendor='Intel'>n270</model>
<model usable='yes' vendor='unknown'>kvm64</model>
<model usable='yes' vendor='unknown'>kvm32</model>
<model usable='yes' vendor='Intel'>coreduo</model>
<model usable='yes' vendor='Intel'>core2duo</model>
<model usable='yes' vendor='AMD'>athlon</model>
<model usable='no' vendor='Intel' blockers='spec-ctrl'>Westmere-IBRS</model>
<model usable='yes' vendor='Intel'>Westmere</model>
<model usable='no' vendor='Intel' blockers='x2apic,tsc-deadline,rdseed,sha-ni,gfni,cldemote,movdiri,movdir64b,spec-ctrl,arch-capabilities,core-capability,ssbd,3dnowprefetch,xsavec,split-lock-detect'>Snowridge</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,avx2,invpcid,avx512f,avx512dq,rdseed,avx512cd,avx512bw,avx512vl,spec-ctrl,3dnowprefetch,xsavec'>Skylake-Server-noTSX-IBRS</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,hle,avx2,invpcid,rtm,avx512f,avx512dq,rdseed,avx512cd,avx512bw,avx512vl,spec-ctrl,3dnowprefetch,xsavec'>Skylake-Server-IBRS</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,hle,avx2,invpcid,rtm,avx512f,avx512dq,rdseed,avx512cd,avx512bw,avx512vl,3dnowprefetch,xsavec'>Skylake-Server</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,avx2,invpcid,rdseed,spec-ctrl,3dnowprefetch,xsavec'>Skylake-Client-noTSX-IBRS</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,hle,avx2,invpcid,rtm,rdseed,spec-ctrl,3dnowprefetch,xsavec'>Skylake-Client-IBRS</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,hle,avx2,invpcid,rtm,rdseed,3dnowprefetch,xsavec'>Skylake-Client</model>
<model usable='no' vendor='Intel' blockers='x2apic,tsc-deadline,avx,spec-ctrl'>SandyBridge-IBRS</model>
<model usable='no' vendor='Intel' blockers='x2apic,tsc-deadline,avx'>SandyBridge</model>
<model usable='yes' vendor='Intel'>Penryn</model>
<model usable='no' vendor='AMD' blockers='fma,avx,f16c,misalignsse,3dnowprefetch,xop,fma4,tbm,nrip-save'>Opteron_G5</model>
<model usable='no' vendor='AMD' blockers='avx,misalignsse,3dnowprefetch,xop,fma4,nrip-save'>Opteron_G4</model>
<model usable='no' vendor='AMD' blockers='misalignsse'>Opteron_G3</model>
<model usable='yes' vendor='AMD'>Opteron_G2</model>
<model usable='yes' vendor='AMD'>Opteron_G1</model>
<model usable='no' vendor='Intel' blockers='spec-ctrl'>Nehalem-IBRS</model>
<model usable='yes' vendor='Intel'>Nehalem</model>
<model usable='no' vendor='Intel' blockers='x2apic,tsc-deadline,avx,f16c,spec-ctrl'>IvyBridge-IBRS</model>
<model usable='no' vendor='Intel' blockers='x2apic,tsc-deadline,avx,f16c'>IvyBridge</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,avx2,invpcid,avx512f,avx512dq,rdseed,avx512cd,avx512bw,avx512vl,avx512vbmi,avx512vbmi2,gfni,vaes,vpclmulqdq,avx512vnni,avx512bitalg,avx512-vpopcntdq,spec-ctrl,ssbd,3dnowprefetch,wbnoinvd,xsavec'>Icelake-Server-noTSX</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,hle,avx2,invpcid,rtm,avx512f,avx512dq,rdseed,avx512cd,avx512bw,avx512vl,avx512vbmi,avx512vbmi2,gfni,vaes,vpclmulqdq,avx512vnni,avx512bitalg,avx512-vpopcntdq,spec-ctrl,ssbd,3dnowprefetch,wbnoinvd,xsavec'>Icelake-Server</model>
<model usable='no' deprecated='yes' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,avx2,invpcid,rdseed,avx512vbmi,avx512vbmi2,gfni,vaes,vpclmulqdq,avx512vnni,avx512bitalg,avx512-vpopcntdq,spec-ctrl,ssbd,3dnowprefetch,wbnoinvd,xsavec'>Icelake-Client-noTSX</model>
<model usable='no' deprecated='yes' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,hle,avx2,invpcid,rtm,rdseed,avx512vbmi,avx512vbmi2,gfni,vaes,vpclmulqdq,avx512vnni,avx512bitalg,avx512-vpopcntdq,spec-ctrl,ssbd,3dnowprefetch,wbnoinvd,xsavec'>Icelake-Client</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,avx2,invpcid,spec-ctrl'>Haswell-noTSX-IBRS</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,avx2,invpcid'>Haswell-noTSX</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,hle,avx2,invpcid,rtm,spec-ctrl'>Haswell-IBRS</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,hle,avx2,invpcid,rtm'>Haswell</model>
<model usable='no' vendor='AMD' blockers='fma,avx,f16c,avx2,rdseed,sha-ni,rdpid,fxsr-opt,misalignsse,3dnowprefetch,osvw,topoext,perfctr-core,clzero,xsaveerptr,wbnoinvd,ibpb,amd-stibp,nrip-save,xsavec,xsaves'>EPYC-Rome</model>
<model usable='no' vendor='AMD' blockers='fma,pcid,avx,f16c,avx2,invpcid,rdseed,sha-ni,rdpid,fsrm,fxsr-opt,misalignsse,3dnowprefetch,osvw,topoext,perfctr-core,clzero,xsaveerptr,wbnoinvd,ibpb,ibrs,amd-stibp,amd-ssbd,nrip-save,xsavec,xsaves'>EPYC-Milan</model>
<model usable='no' vendor='AMD' blockers='fma,avx,f16c,avx2,rdseed,sha-ni,fxsr-opt,misalignsse,3dnowprefetch,osvw,topoext,ibpb,nrip-save,xsavec'>EPYC-IBPB</model>
<model usable='no' vendor='AMD' blockers='fma,avx,f16c,avx2,rdseed,sha-ni,fxsr-opt,misalignsse,3dnowprefetch,osvw,topoext,nrip-save,xsavec'>EPYC</model>
<model usable='no' vendor='Hygon' blockers='fma,avx,f16c,avx2,rdseed,fxsr-opt,misalignsse,3dnowprefetch,osvw,topoext,ibpb,nrip-save,xsavec'>Dhyana</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,hle,avx2,invpcid,rtm,avx512f,avx512dq,rdseed,avx512cd,avx512bw,avx512vl,avx512vnni,spec-ctrl,stibp,arch-capabilities,ssbd,avx512-bf16,3dnowprefetch,xsavec,rdctl-no,ibrs-all,skip-l1dfl-vmentry,mds-no,pschange-mc-no,taa-no'>Cooperlake</model>
<model usable='yes' vendor='Intel'>Conroe</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,avx2,invpcid,avx512f,avx512dq,rdseed,avx512cd,avx512bw,avx512vl,avx512vnni,spec-ctrl,arch-capabilities,ssbd,3dnowprefetch,xsavec,rdctl-no,ibrs-all,skip-l1dfl-vmentry,mds-no'>Cascadelake-Server-noTSX</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,hle,avx2,invpcid,rtm,avx512f,avx512dq,rdseed,avx512cd,avx512bw,avx512vl,avx512vnni,spec-ctrl,ssbd,3dnowprefetch,xsavec'>Cascadelake-Server</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,avx2,invpcid,rdseed,spec-ctrl,3dnowprefetch'>Broadwell-noTSX-IBRS</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,avx2,invpcid,rdseed,3dnowprefetch'>Broadwell-noTSX</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,hle,avx2,invpcid,rtm,rdseed,spec-ctrl,3dnowprefetch'>Broadwell-IBRS</model>
<model usable='no' vendor='Intel' blockers='fma,pcid,x2apic,tsc-deadline,avx,f16c,hle,avx2,invpcid,rtm,rdseed,3dnowprefetch'>Broadwell</model>
<model usable='yes' vendor='unknown'>486</model>
I think we need to expose this in a different way, using the CPU baseline
APIs. THese already have a VIR_CPU_BASELINE_EXPAND_FEATURES flag. We
should add a further VIR_CPU_BASELINE_BLOCKED_FEATURES flag to it.
With regards,
Daniel
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